公开(公告)号：US10304800B2

公开(公告)日：2019-05-28

申请号：US15800962

申请日：2017-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Weiming Chris Chen ,  Ting-Yu Yeh ,  Chia-Hsin Chen ,  Tu-Hao Yu ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: H01L23/02 ,  H01L21/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L23/498 ,  H01L25/16

Abstract: A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a first die disposed over the second surface of the first substrate; a plurality of first conductive bumps disposed between the first die and the first substrate; a molding disposed over the first substrate and surrounding the first die and the plurality of first conductive bumps; a second substrate disposed below the first surface of the first substrate; a plurality of second conductive bumps disposed between the first substrate and the second substrate; and a second die disposed between the first substrate and the second substrate.

公开(公告)号：US20190148329A1

公开(公告)日：2019-05-16

申请号：US15813538

申请日：2017-11-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L25/18 ,  H01L25/00

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US20150221611A1

公开(公告)日：2015-08-06

申请号：US14257833

申请日：2014-04-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shin-Puu Jeng ,  Wen-Chih Chiou ,  Tu-Hao Yu ,  Hung-Jung Tu ,  Yu-Liang Lin ,  Shih-Hui Wang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/09 ,  H01L24/17 ,  H01L24/81 ,  H01L24/89 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08235 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13811 ,  H01L2224/13816 ,  H01L2224/13839 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/80805 ,  H01L2224/81805 ,  H01L2224/83 ,  H01L2224/83192 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/12042 ,  H01L2924/151 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/161 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes coupling integrated circuit dies to a substrate, and disposing a molding material around the integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies.

Abstract translation: 公开了封装半导体器件和封装半导体器件的方法。 在一些实施例中，封装半导体器件的方法包括将集成电路管芯耦合到衬底，以及将模制材料设置在集成电路管芯周围。 盖层设置在成型材料和多个集成电路管芯之上。

公开(公告)号：US11508696B2

公开(公告)日：2022-11-22

申请号：US16716225

申请日：2019-12-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Weiming Chris Chen ,  Tu-Hao Yu ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/50 ,  H01L23/498 ,  H01L25/00 ,  H01L23/538 ,  H01L25/16 ,  H01L49/02 ,  H01L23/13

Abstract: A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The second electronic component is between the first electronic component and the third electronic component. The first interconnection structures are between and electrically connected to the first electronic component and the second electronic component. Each of the first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between and electrically connected to the second electronic component and the third electronic component.

公开(公告)号：US11139282B2

公开(公告)日：2021-10-05

申请号：US16046713

申请日：2018-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kuo-Chiang Ting ,  Tu-Hao Yu ,  Ting-Yu Yeh ,  Chia-Hao Hsu ,  Weiming Chris Chen ,  Wan-Yu Lee ,  Yu-Jie Su

IPC: H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L23/00 ,  H01L25/04 ,  H01L25/065

Abstract: A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.

公开(公告)号：US20200027851A1

公开(公告)日：2020-01-23

申请号：US16575573

申请日：2019-09-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US12080638B2

公开(公告)日：2024-09-03

申请号：US17816376

申请日：2022-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Pin-Tso Lin ,  Chia-Hsin Chen

IPC: H01L23/498 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49894 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3171 ,  H01L24/09 ,  H01L24/13 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/17505 ,  H01L2924/3511

Abstract: A semiconductor device includes a dielectric interposer, a first redistribution layer, a second redistribution layer and conductive structures. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first redistribution layer and the second redistribution layer. Each of the conductive structures has a tapered profile. A width of each of the conductive structures proximal to the first redistribution layer is narrower than a width of each of the conductive structure proximal to the second redistribution layer.

公开(公告)号：US12062590B2

公开(公告)日：2024-08-13

申请号：US16725189

申请日：2019-12-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ting-Yu Yeh ,  Chia-Hao Hsu ,  Weiming Chris Chen ,  Kuo-Chiang Ting ,  Tu-Hao Yu ,  Shang-Yun Hou

IPC: H01L23/373 ,  H01L21/66 ,  H01L23/00 ,  H01L27/06

CPC classification number: H01L23/3735 ,  H01L22/32 ,  H01L23/562 ,  H01L24/17 ,  H01L27/0688 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.

公开(公告)号：US11476184B2

公开(公告)日：2022-10-18

申请号：US16723434

申请日：2019-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Pin-Tso Lin ,  Chia-Hsin Chen

IPC: H01L23/498 ,  H01L21/683 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor device includes a dielectric interposer, a first interconnection layer, an electronic component, a plurality of electrical conductors and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first interconnection layer is over the first surface of the dielectric interposer. The electronic component is over and electrically connected to the first interconnection layer. The electrical conductors are over the second surface of the dielectric interposer. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first interconnection layer and the electrical conductors.

公开(公告)号：US10720401B2

公开(公告)日：2020-07-21

申请号：US16575573

申请日：2019-09-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L23/31

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.