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公开(公告)号：US20190148329A1
公开(公告)日：2019-05-16
申请号：US15813538
申请日：2017-11-15
Inventor： Kuo-Chiang Ting , Chi-Hsi Wu , Shang-Yun Hou , Tu-Hao Yu , Chia-Hao Hsu , Ting-Yu Yeh
IPC: H01L23/00 , H01L23/538 , H01L21/48 , H01L23/498 , H01L25/18 , H01L25/00
Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
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2.发明授权公开(公告)号：US09869934B2
公开(公告)日：2018-01-16
申请号：US15194118
申请日：2016-06-27
Inventor： Chia-Ching Huang , Tsung-Yu Chen , Chia-Hao Hsu , Shinn-Sheng Yu , Chia-Chen Chen
CPC classification number: G03F7/70033 , H05G2/005 , H05G2/008
Abstract: The present disclosure provides an extreme ultraviolet (EUV) lithography system. The EUV lithography system includes a collector having a coating surface designed to collect and reflect EUV radiation; a gas supply module; and a gas pipeline integrated with the collector and connected to the gas supply module. The gas pipeline includes inward and outward entrances into the collector. The inward and outward entrances are configured and operable to form a gas curtain on the coating surface of the collector.
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公开(公告)号：US20160349609A1
公开(公告)日：2016-12-01
申请号：US14724397
申请日：2015-05-28
Inventor： Chia-Chun Chung , Chia-Hao Hsu , Chih-Tsung Shih
Abstract: A method includes providing a carrier wafer, forming an indented portion on the carrier wafer, the indented portion having a sloped portion at an edge of the indented portion, bonding a pellicle wafer on the carrier wafer so as to form an open area within the indented portion, patterning the pellicle wafer to form a pellicle membrane over the indented portion and a pellicle membrane support structure over the sloped portion, and applying a mechanical force to disconnect the pellicle membrane from the pellicle wafer.
Abstract translation: 一种方法包括提供载体晶片，在载体晶片上形成凹陷部分，凹陷部分在凹入部分的边缘处具有倾斜部分，将薄膜晶片接合在载体晶片上，以便在凹槽内形成开放区域 图案化薄膜晶片以在凹陷部分上形成防护薄膜组件，并且在倾斜部分上方形成防护薄膜支撑结构，并且施加机械力以使防护薄膜组件与防护薄膜组件切断。
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公开(公告)号：US09128384B2
公开(公告)日：2015-09-08
申请号：US13673729
申请日：2012-11-09
Inventor： Yu Chao Lin , Chia-Hao Hsu , Kuo-Yu Wu , Chia-Jen Chen , Chao-Cheng Chen
IPC: H01L21/66 , H01L21/312 , G03F7/40 , G03F7/00 , G03F7/075 , G03F7/09 , G03F7/095 , H01L21/033 , H01L21/3213
CPC classification number: H01L22/12 , G03F7/0035 , G03F7/0752 , G03F7/091 , G03F7/095 , G03F7/40 , G03F7/70633 , H01L21/0276 , H01L21/0337 , H01L21/31144 , H01L21/32139
Abstract: An embodiment of a method of forming a substrate pattern including forming a bottom layer and an overlying middle layer on the substrate. A photo resist pattern is formed on the middle layer. An etch coating layer is deposited on the photo resist pattern. The etch coating layer and the photo resist pattern are used as a masking element to pattern at least one of the middle layer and the bottom layer. The substrate is etched to form the substrate pattern using the at least one of the patterned middle layer and the patterned bottom layer as a masking element. The substrate pattern may be used as an element of an overlay measurement process.
Abstract translation: 一种形成衬底图案的方法的实施例，包括在衬底上形成底层和上覆中间层。 在中间层上形成光刻胶图形。 蚀刻涂层沉积在光刻胶图案上。 蚀刻涂层和光刻胶图案用作屏蔽元件以图案化中间层和底层中的至少一个。 使用图案化中间层和图案化底层中的至少一个作为掩模元件来蚀刻衬底以形成衬底图案。 衬底图案可以用作覆盖测量过程的元件。
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5.发明授权Semiconductor structure for extreme ultraviolet electrostatic chuck with reduced clamping effect 有权具有减少夹紧效应的极紫外线静电卡盘的半导体结构公开(公告)号：US09117830B2
公开(公告)日：2015-08-25
申请号：US14296519
申请日：2014-06-05
Inventor： Chia-Hao Hsu , Chia-Chen Chen , Tzung-Chi Fu , Tzu-Wei Kao , Yu Chao Lin
IPC: H01L23/00 , H01L29/06 , H01L29/34 , H01L21/3215 , G03F7/20 , H01L21/265 , H01L21/683
CPC classification number: H01L23/562 , G03F7/70708 , H01L21/26506 , H01L21/32155 , H01L21/6831 , H01L29/0603 , H01L29/34 , H01L2924/0002 , H01L2924/00
Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate.
Abstract translation: 本公开提供了半导体结构的一个实施例。 半导体结构包括具有前表面和后表面的半导体衬底; 集成电路特征形成在半导体衬底的前表面上; 以及设置在半导体衬底的背面上的多晶硅层。
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Patent Agency Ranking
6.发明申请SEMICONDUCTOR STRUCTURE FOR EXTREME ULTRAVIOLET ELECTROSTATIC CHUCK WITH REDUCED CLAMPING EFFECT 有权具有减少钳位效应的极端超紫外线静电切片的半导体结构公开(公告)号：US20140284604A1
公开(公告)日：2014-09-25
申请号：US14296519
申请日：2014-06-05
Inventor： Chia-Hao Hsu , Chia-Chen Chen , Tzung-Chi Fu , Tzu-Wei Kao , Yu Chao Lin
CPC classification number: H01L23/562 , G03F7/70708 , H01L21/26506 , H01L21/32155 , H01L21/6831 , H01L29/0603 , H01L29/34 , H01L2924/0002 , H01L2924/00
Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate.
Abstract translation: 本公开提供了半导体结构的一个实施例。 半导体结构包括具有前表面和后表面的半导体衬底; 集成电路特征形成在半导体衬底的前表面上; 以及设置在半导体衬底的背面上的多晶硅层。
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公开(公告)号：US11476184B2
公开(公告)日：2022-10-18
申请号：US16723434
申请日：2019-12-20
Inventor： Kuo-Chiang Ting , Chi-Hsi Wu , Shang-Yun Hou , Tu-Hao Yu , Chia-Hao Hsu , Pin-Tso Lin , Chia-Hsin Chen
IPC: H01L23/498 , H01L21/683 , H01L23/31 , H01L21/56 , H01L23/00
Abstract: A semiconductor device includes a dielectric interposer, a first interconnection layer, an electronic component, a plurality of electrical conductors and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first interconnection layer is over the first surface of the dielectric interposer. The electronic component is over and electrically connected to the first interconnection layer. The electrical conductors are over the second surface of the dielectric interposer. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first interconnection layer and the electrical conductors.
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公开(公告)号：US10720401B2
公开(公告)日：2020-07-21
申请号：US16575573
申请日：2019-09-19
Inventor： Kuo-Chiang Ting , Chi-Hsi Wu , Shang-Yun Hou , Tu-Hao Yu , Chia-Hao Hsu , Ting-Yu Yeh
IPC: H01L23/00 , H01L21/56 , H01L21/683 , H01L21/48 , H01L23/498 , H01L23/538 , H01L25/18 , H01L25/00 , H01L23/31
Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
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公开(公告)号：US20240387465A1
公开(公告)日：2024-11-21
申请号：US18784867
申请日：2024-07-25
Inventor： Chia-Hao Hsu , Yung-Chi Lin , Wen-Chih Chiou
IPC: H01L25/065 , H01L23/00 , H01L23/48 , H01L25/00
Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.
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公开(公告)号：US10684552B2
公开(公告)日：2020-06-16
申请号：US15971181
申请日：2018-05-04
Inventor： Yen-Cheng Lu , Chia-Hao Hsu , Shinn-Sheng Yu , Chia-Chen Chen , Jeng-Horng Chen , Anthony Yen
Abstract: Various methods are disclosed herein for reducing (or eliminating) printability of mask defects during lithography processes. An exemplary method includes performing a first lithography exposing process and a second lithography exposing process using a mask to respectively image a first set of polygons oriented substantially along a first direction and a second set of polygons oriented substantially along a second direction on a target. During the first lithography exposing process, a phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the first direction and a third direction that is different than the first direction. During the second lithography exposing process, the phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the second direction and a fourth direction that is different than the third direction.
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