公开(公告)号：US12132028B2

公开(公告)日：2024-10-29

申请号：US17698976

申请日：2022-03-18

Applicant: Amazon Technologies, Inc.

Inventor： Bassam Abdel-Dayem ,  Thomas A. Volpe

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/64 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L23/5386 ,  H01L23/642 ,  H01L25/50

Abstract: A semiconductor package can include a capacitance die. The package can have multiple dice (e.g., logic die, memory die) mounted on a substrate. Each die can include a power domain. The dice can be distributed on the substrate such that an extra space is present on the substrate between at least some of the dice. For example, an extra space may be present between two dice, at a corner of the substrate, or other locations. The extra space can disrupt a coplanarity of the semiconductor package. The capacitance die can be located in the extra space so as to establish the coplanarity with the other dice. The capacitance die can include a capacitor array electrically coupled to multiple power domains of the plurality of dice.

公开(公告)号：US11729300B2

公开(公告)日：2023-08-15

申请号：US17163211

申请日：2021-01-29

Applicant: Amazon Technologies, Inc.

Inventor： Thomas A. Volpe ,  Timothy David Gasser ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Vithal Dattatraya Shirodkar

IPC: H04L69/22 ,  H04L45/7453

CPC classification number: H04L69/22 ,  H04L45/7453

Abstract: Programmatically defined fields of metadata for a network packet may be generated. Instructions indicating different portions of data from different headers of a network packet may be stored at a packet processor. When a network packet is received, the different portions of the data may be extracted from the different headers of the packet according to the instructions and provided to other stages of the packet processor for processing. Different portions of the same programmatically defined field may be utilized at different stages in the packet processor. The programmatically defined field may be used to generate a hash value that selects an entry in a lookup table describing a forwarding decision for a network packet.

公开(公告)号：US10956248B1

公开(公告)日：2021-03-23

申请号：US16200602

申请日：2018-11-26

Applicant: Amazon Technologies, Inc.

Inventor： Thomas A. Volpe ,  Raymond S. Whiteside

IPC: G06F11/07

Abstract: An integrated circuit configured to execute program instructions can generate, based on a configuration, any combination of a notification message, a halt signal, or an interrupt signal for a condition detected in the integrated circuit. The detected condition can be an error condition or a non-error condition. The notification message for the condition may be written to memory accessible by a host processor. The non-error condition may be used by the host processor to monitor internal states of the integrated circuit. The halt signal may be used to stop the integrated circuit from executing the instructions.

公开(公告)号：US10949321B1

公开(公告)日：2021-03-16

申请号：US16200620

申请日：2018-11-26

Applicant: Amazon Technologies, Inc.

Inventor： Thomas A. Volpe ,  Alwood Patrick Williams, III ,  Brian Robert Silver

IPC: G06F11/30 ,  G06F11/34 ,  G01R31/317 ,  G06F11/07

Abstract: Operational management of an integrated circuit device can be performed by a microcontroller based on information associated with the notification messages generated by the integrated circuit device. The notification messages may include timestamps and metadata for different notification types which can be used to build a timeline. The microcontroller may use the information to monitor the operational health and performance of the integrated circuit device or can communicate this information to a remote management server.

公开(公告)号：US10860397B1

公开(公告)日：2020-12-08

申请号：US16297467

申请日：2019-03-08

Applicant: Amazon Technologies, Inc.

Inventor： Brian Robert Silver ,  Kun Xu ,  Alwood Patrick Williams ,  Thomas A. Volpe

IPC: H04L7/00 ,  G06F9/54 ,  G06F9/50

Abstract: A computer system has a memory configured for sharing data between a first application and a second application. The memory includes a metadata region and a data region. The metadata region includes metadata that indicates how data being communicated between the first application and the second application is to be interpreted. The metadata also indicates whether the data can be found in the metadata itself or in a particular location in the data region. Each application can be assigned its own memory location containing a flag that can be set in order to indicate to the other application that the memory is ready to be accessed by the other application. The memory location can be implemented using a hardware register or in memory, either the same memory that includes the metadata and data regions or on a separate memory.

公开(公告)号：US10817177B1

公开(公告)日：2020-10-27

申请号：US16283559

申请日：2019-02-22

Applicant: Amazon Technologies, Inc.

Inventor： Thomas A. Volpe ,  Mark Anthony Banse

IPC: G06F12/00 ,  G06F3/06

Abstract: Disclosed herein are methods and apparatuses related to the use of counter tables. A counter table can comprise a plurality of lower-level counters and an upper-level counter. A range of values capable of being represented by a lower-level counter from the plurality of lower-level counters can be enlarged by associating the lower-level counter with the upper-level counter. A counter table can be associated with a network device.

公开(公告)号：US10725957B1

公开(公告)日：2020-07-28

申请号：US16460897

申请日：2019-07-02

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Thomas A. Volpe ,  Nafea Bshara ,  Yaniv Shapira ,  Adi Habusha

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16

Abstract: A plurality of system on chips (SoCs) in a server computer can be coupled to a plurality of memory agents (MAs) via respective Serializer/Deserializer (SerDes) interfaces. Each of the plurality of MAs can include one or more memory controllers to communicate with a memory coupled to the respective MA, and globally addressable by each of the SoCs. Each of the plurality of SoCs can access the memory coupled to any of the MAs in uniform number of hops using the respective SerDes interfaces. Different types of memories, e.g., volatile memory, persistent memory, can be supported.

公开(公告)号：US10404674B1

公开(公告)日：2019-09-03

申请号：US15445190

申请日：2017-02-28

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Thomas A. Volpe ,  Adi Habusha ,  Yaniv Shapira

IPC: G06F12/14 ,  G06F9/455 ,  H04L29/06 ,  H04L9/08

Abstract: Efficient memory management can be provided in a multi-tenant virtualized environment by encrypting data to be written in memory by a virtual machine using a cryptographic key specific to the virtual machine. Encrypting data associated with multiple virtual machines using a cryptographic key unique to each virtual machine can minimize exposure of the data stored in the memory shared by the multiple virtual machines. Thus, some embodiments can eliminate write cycles to the memory that are generally used to initialize the memory before a virtual machine can write data to the memory if the memory was used previously by another virtual machine.

公开(公告)号：US10228852B1

公开(公告)日：2019-03-12

申请号：US15081628

申请日：2016-03-25

Applicant: Amazon Technologies, Inc.

Inventor： Thomas A. Volpe ,  Mark Anthony Banse

IPC: G06F12/00 ,  G06F3/06

Abstract: Disclosed herein are methods and apparatuses related to the use of counter tables. A counter table can comprise a plurality of lower-level counters and an upper-level counter. A range of values capable of being represented by a lower-level counter from the plurality of lower-level counters can be enlarged by associating the lower-level counter with the upper-level counter. A counter table can be associated with a network device.

公开(公告)号：US10164759B1

公开(公告)日：2018-12-25

申请号：US15377939

申请日：2016-12-13

Applicant: Amazon Technologies, Inc.

Inventor： Thomas A. Volpe

IPC: H04J3/06 ,  H04L7/00

Abstract: Provided are systems and methods for implementing a reliable precision time architecture in a network device. In various implementations, a first port of the network device can be configured to synchronize to a first network time from the network. A second port can be configure to receive the first network time from the first port, and further provide the first network time to the network. A third port of the network device can further be configured to synchronize to a second network time from the network. A fourth port can be configured to receive the second network time from the third port, and provide the second network time to the network. The network device can further be configured to use the first network time as a current time.