公开(公告)号：US20220230958A1

公开(公告)日：2022-07-21

申请号：US17716937

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Poh Boon KHOO ,  Eng Huat GOH ,  Amruthavalli Pallavi ALUR ,  Debendra MALLIK

IPC: H01L23/522 ,  H01L23/00

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

公开(公告)号：US20240106139A1

公开(公告)日：2024-03-28

申请号：US17955369

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Eng Huat GOH ,  Poh Boon KHOO ,  Chin Mian CHOONG ,  Jooi Wah WONG ,  Jia Yun WONG

IPC: H01R12/57 ,  H01L25/065 ,  H01L25/10 ,  H01R12/52 ,  H01R12/79 ,  H01R13/03 ,  H01R13/508 ,  H01R43/20

CPC classification number: H01R12/57 ,  H01L25/0652 ,  H01L25/105 ,  H01R12/526 ,  H01R12/79 ,  H01R13/03 ,  H01R13/508 ,  H01R43/205 ,  H01L24/16

Abstract: Embodiments herein relate to systems, apparatuses, or processes for a connector for a modular memory package that includes one or more memory dies on a substrate, where the connector directly electrically couples electrical contacts at an edge and on each side the substrate of the memory package to electrical contacts at an edge and on each side of another substrate that includes a compute die. The connector may include a first plurality of leads that are substantially parallel with each other, and a second plurality of leads that are substantially parallel with each other that are below the first plurality of leads and electrically couple the two substrates. Other embodiments may be described and/or claimed.

公开(公告)号：US20240071948A1

公开(公告)日：2024-02-29

申请号：US17895112

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Eng Huat GOH ,  Poh Boon KHOO ,  Nurul Khalidah YUSOP ,  Saw Beng TEOH ,  Chan Kim LEE

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/367 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package is provided including: a package substrate with a top surface, wherein the top surface extends to a peripheral side surface of the package substrate; a stiffener with a lateral portion and a basket portion, wherein the lateral portion is positioned over the top surface of the package substrate and the basket portion overhangs from the top surface of the package substrate adjacent to the peripheral side surface of the package substrate; at least one semiconductor die positioned in the basket portion of the stiffener; and at least one wire attached to the at least one semiconductor die and extending out of the basket portion of the stiffener.

公开(公告)号：US20230397323A1

公开(公告)日：2023-12-07

申请号：US17834641

申请日：2022-06-07

Applicant: Intel Corporation

Inventor： Min Suet LIM ,  Tin Poay CHUAH ,  Yew San LIM ,  Jeff KU ,  Twan Sing LOO ,  Poh Boon KHOO ,  Jiun Hann SIR

IPC: H05K1/02 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18 ,  H05K3/22 ,  H01L23/42

CPC classification number: H05K1/0204 ,  H01L23/3675 ,  H01L25/0652 ,  H01L25/18 ,  H05K3/22 ,  H01L23/42 ,  H01L2224/32225 ,  H01L24/32

Abstract: Embodiments disclosed herein include a printed circuit board (PCB). In an embodiment, the PCB comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, a first slot is through a thickness of the substrate, and a second slot is through the thickness of the substrate, where the first slot is parallel to the second slot. In an embodiment, a metal plate is provided on the PCB. In an embodiment the metal plate comprises a first portion over the first surface of the substrate between the first slot and the second slot, a second portion connected to the first portion, wherein the second portion is in the first slot, and a third portion connected to the first portion, wherein the third portion is in the second slot.

公开(公告)号：US20240113033A1

公开(公告)日：2024-04-04

申请号：US17956753

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Eng Huat GOH ,  Jiun Hann SIR ,  Poh Boon KHOO ,  Hazwani JAFFAR ,  Hooi San LAM

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes a die, which may be a processor die, coupled with a first side of a substrate and one or more dies, which may be one or more memory dies, that are coupled with a second side of the substrate opposite the first side of the substrate. All or part of the memory dies may be directly below the die with respect to a plane of the substrate and may be partially or completely within a molding. Other embodiments may be described and/or claimed.

公开(公告)号：US20230395524A1

公开(公告)日：2023-12-07

申请号：US17833580

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Eng Huat GOH ,  Jiun Hann SIR ,  Chee Kheong YOON ,  Telesphor KAMGAING ,  Min Suet LIM ,  Kavitha NAGARAJAN ,  Chu Aun LIM

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/66 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L24/32 ,  H01L24/29 ,  H01L23/66 ,  H01L24/27 ,  H01L24/16 ,  H01L24/73 ,  H01L23/49822 ,  H01L2224/27515 ,  H01L2224/32227 ,  H01L2224/73204 ,  H01L2224/16235 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/3511 ,  H01L2924/3025 ,  H01L2924/2027 ,  H01L2924/1421 ,  H01L2224/32237 ,  H01L2224/29018 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2924/0781

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die coupled to the package substrate. In an embodiment, a stiffener is around the die and over the package substrate. In an embodiment, an electrically non-conductive underfill is around first level interconnects (FLIs) between the package substrate and the die. In an embodiment, an electrically conductive layer is around the non-conductive underfill.

公开(公告)号：US20210202380A1

公开(公告)日：2021-07-01

申请号：US17200700

申请日：2021-03-12

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Poh Boon KHOO ,  Eng Huat GOH ,  Amruthavalli Pallavi ALUR ,  Debendra MALLIK

IPC: H01L23/522 ,  H01L23/00

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

公开(公告)号：US20240355792A1

公开(公告)日：2024-10-24

申请号：US18137360

申请日：2023-04-20

Applicant: Intel Corporation

Inventor： Poh Boon KHOO ,  Jiun Hann SIR ,  Eng Huat GOH ,  Hooi San LAM ,  Hazwani JAFFAR

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H10B80/00 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Embodiments disclosed herein include electronic packages. In an example, an electronic package includes a package substrate. A die is coupled to the package substrate. The electronic package also includes a memory stack. The memory stack includes a die stack structure coupled to a substrate. The substrate is coupled to and is extending laterally beyond the package substrate. The die stack structure includes a stack of dies and through vias in a mold layer. The die stack structure is laterally spaced apart from the package substrate.

公开(公告)号：US20220173027A1

公开(公告)日：2022-06-02

申请号：US17671478

申请日：2022-02-14

Applicant: Intel Corporation

Inventor： Eng Huat GOH ,  Jiun Hann SIR ,  Min Suet LIM

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/50

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package. For instance, in accordance with one embodiment, there is a substrate package having embodied therein a functional silicon die at a top layer of the substrate package; a solder resist layer beneath the functional silicon die of the substrate package; a plurality of die bumps at a bottom surface of the functional silicon die, the plurality of die bumps electrically interfacing the functional silicon die to a substrate through a plurality of solder balls at a top surface of the solder resist layer; each of the plurality of die bumps electrically interfaced to a nickel pad at least partially within the solder resist layer and beneath the solder balls; each of the plurality of die bumps electrically interfaced through the nickel pads to a conductive pad exposed at a bottom surface of the solder resist layer; and in which each of the conductive pads exposed at the bottom surface of the solder resist layer are electrically interfaced to an electrical trace at the substrate of the substrate package. Other related embodiments are disclosed.

公开(公告)号：US20190214338A1

公开(公告)日：2019-07-11

申请号：US16328231

申请日：2016-09-14

Applicant: Intel Corporation

Inventor： Eng Huat GOH ,  Jiun Hann SIR ,  Min Suet LIM ,  Shawna M. LIFF ,  Feras EID

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/00 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/552 ,  H01L23/562

Abstract: Semiconductor packages that mitigate warpage and/or other types or mechanical deformation of package substrates are provided. In some embodiments, a package substrate can include a peripheral conductive region having an assembly of rigid conductive members, such as metal layers, metal interconnects, or a combination thereof. The peripheral conductive region can be integrated into the package substrate during the manufacturing of the package substrate. In some implementations, lithographically defined conductive members can be leveraged to form extended conductive layers that can provide increased stiffness compared to nearly cylindrical conductive vias. Non-peripheral conductive regions also can be integrated into a semiconductor package in order to reduce specific patterns of mechanical deformations and/or to provide other functionality, such as electromagnetic interference (EMI) shielding.