- 专利标题: CO-DEPOSITION OF TITANIUM AND SILICON FOR IMPROVED SILICON GERMANIUM SOURCE AND DRAIN CONTACTS
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申请号: US17358436申请日: 2021-06-25
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公开(公告)号: US20220416032A1公开(公告)日: 2022-12-29
- 发明人: Debaleena Nandi , Chi-Hing Choi , Gilbert Dewey , Harold Kennel , Omair Saadat , Jitendra Kumar Jha , Adedapo Oni , Nazila Haratipour , Anand Murthy , Tahir Ghani
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H01L29/417
- IPC分类号: H01L29/417 ; H01L27/088 ; H01L29/161 ; H01L21/8234 ; H01L21/28 ; H01L21/768
摘要:
Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.
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