公开(公告)号：US12058847B2

公开(公告)日：2024-08-06

申请号：US16888910

申请日：2020-06-01

申请人： Intel Corporation

发明人： Prashant Majhi ,  Abhishek A. Sharma ,  Charles Kuo ,  Brian S. Doyle ,  Urusa Shahriar Alaan ,  Van H Le ,  Elijah V. Karpov ,  Kaan Oguz ,  Arnab Sen Gupta

IPC分类号： H10B12/00 ,  H01L25/065

CPC分类号： H10B12/30 ,  H01L25/0657

摘要： Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.

公开(公告)号：US20240105810A1

公开(公告)日：2024-03-28

申请号：US17952161

申请日：2022-09-23

申请人： Intel Corporation

发明人： Rachel A. Steinhardt ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Punyashloka Debashis ,  I-Cheng Tung ,  Gauri Auluck

IPC分类号： H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/516 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7831

摘要： In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

公开(公告)号：US11777029B2

公开(公告)日：2023-10-03

申请号：US16455567

申请日：2019-06-27

申请人： Intel Corporation

发明人： Nazila Haratipour ,  I-Cheng Tung ,  Abhishek A. Sharma ,  Arnab Sen Gupta ,  Van Le ,  Matthew V. Metz ,  Jack Kavalieros ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/42364 ,  H01L29/66666

摘要： A vertical transistor structure includes a material stack having a source material, a drain material, and a channel material therebetween. The vertical transistor structure further includes a gate electrode adjacent to a sidewall of the stack, where the sidewall includes the channel material, and at least a partial thickness of both the source material and the drain material. A gate dielectric is present between the sidewall of the stack and the gate electrode. The vertical transistor structure further includes a first metallization over a first area of the stack above the gate dielectric layer, and in contact with the gate electrode on sidewall of the stack. A second metallization is adjacent to the first metallization, where the second metallization is over a second area of the stack, and in contact with the source material or the drain material.

公开(公告)号：US20230253444A1

公开(公告)日：2023-08-10

申请号：US17666745

申请日：2022-02-08

申请人： Intel Corporation

发明人： Arnab Sen Gupta ,  Kaan Oguz ,  Chia-Ching Lin ,  I-Cheng Tung ,  Sudarat Lee ,  Sou-Chi Chang ,  Matthew V. Metz ,  Scott B. Clendenning ,  Uygar E. Avci ,  Ian A. Young ,  Jason C. Retasket ,  Edward O. Johnson, JR.

IPC分类号： H01L49/02 ,  H01L27/108

CPC分类号： H01L28/65 ,  H01L28/75 ,  H01L27/10829

摘要： Described herein are capacitor devices formed using perovskite insulators. In one example, a perovskite templating material is formed over an electrode, and a perovskite insulator layer is grown over the templating material. The templating material improves the crystal structure and electrical properties in the perovskite insulator layer. One or both electrodes may be ruthenium. In another example, a perovskite insulator layer is formed between two layers of indium tin oxide (ITO), with the ITO layers forming the capacitor electrodes.

公开(公告)号：US11955560B2

公开(公告)日：2024-04-09

申请号：US16914172

申请日：2020-06-26

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Arnab Sen Gupta ,  Travis W. LaJoie ,  Sarah Atanasov ,  Chieh-Jen Ku ,  Bernhard Sell ,  Noriyuki Sato ,  Van Le ,  Matthew Metz ,  Hui Jae Yoo ,  Pei-Hua Wang

IPC分类号： H01L29/66 ,  H01L27/22 ,  H01L29/786 ,  H10B61/00 ,  H10B63/00

CPC分类号： H01L29/7869 ,  H01L29/66969 ,  H10B61/22 ,  H10B63/30

摘要： A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

公开(公告)号：US20240006533A1

公开(公告)日：2024-01-04

申请号：US17856982

申请日：2022-07-02

申请人： Intel Corporation

发明人： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Matthew V. Metz ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC分类号： H01L29/78 ,  H01L29/167

CPC分类号： H01L29/785 ,  H01L29/167

摘要： Contacts to p-type source/drain regions comprise a boride, indium, or gallium metal compound layer. The boride, indium, or gallium metal compound layers can aid in forming thermally stable low resistance contacts. A boride, indium, or gallium metal compound layer is positioned between the source/drain region and the contact metal layer. A boride, indium, or gallium metal compound layer can be used in contacts contacting p-type source/drain regions comprising boron, indium, or gallium as the primary dopant, respectively. The boride, indium, or gallium metal compound layers prevent diffusion of boron, indium, or gallium from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Boride, indium, or gallium metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting contact metal diffusion into source/drain regions.

公开(公告)号：US20230187553A1

公开(公告)日：2023-06-15

申请号：US17546461

申请日：2021-12-09

申请人： Intel Corporation

发明人： Arnab Sen Gupta ,  Gilbert W. Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Scott B. Clendenning ,  Jason C. Retasket ,  Edward O. Johnson, JR.

IPC分类号： H01L29/786 ,  H01L29/66

CPC分类号： H01L29/78618 ,  H01L29/78696 ,  H01L29/66742

摘要： Described herein are integrated circuit devices with source and drain (S/D) contacts with barrier regions. The S/D contacts conduct current to and from semiconductor devices, e.g., to the source and drain regions of a transistor. The barrier regions are formed between the S/D region and an inner conductive structure and reduce the Schottky barrier height between the S/D region and the contact. The barrier regions may include one or more carbon layers and one or more metal layers. A metal layer may include niobium, tantalum, aluminum, or titanium.

公开(公告)号：US11637185B2

公开(公告)日：2023-04-25

申请号：US16141301

申请日：2018-09-25

申请人： Intel Corporation

发明人： Justin Weber ,  Harold Kennel ,  Abhishek Sharma ,  Christopher Jezewski ,  Matthew V. Metz ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Van H. Le ,  Arnab Sen Gupta

IPC分类号： H01L29/36 ,  H01L29/22 ,  H01L29/24 ,  H01L29/47 ,  H01L21/322 ,  H01L29/45 ,  H01L21/02 ,  H01L21/768 ,  H01L29/267

摘要： Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.

公开(公告)号：US20210408291A1

公开(公告)日：2021-12-30

申请号：US16914172

申请日：2020-06-26

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Arnab Sen Gupta ,  Travis W. LaJoie ,  Sarah Atanasov ,  Chieh-Jen Ku ,  Bernhard Sell ,  Noriyuki Sato ,  Van Le ,  Matthew Metz ,  Hui Jae Yoo ,  Pei-Hua Wang

IPC分类号： H01L29/786 ,  H01L27/22 ,  H01L27/24 ,  H01L29/66

摘要： A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

公开(公告)号：US20240120415A1

公开(公告)日：2024-04-11

申请号：US17958362

申请日：2022-10-01

申请人： Intel Corporation

发明人： Scott B. Clendenning ,  Sudarat Lee ,  Kevin P. O'Brien ,  Rachel A. Steinhardt ,  John J. Plombon ,  Arnab Sen Gupta ,  Charles C. Mokhtarzadeh ,  Gauri Auluck ,  Tristan A. Tronic ,  Brandon Holybee ,  Matthew V. Metz ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/778 ,  H01L21/02197 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/78391

摘要： Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.