公开(公告)号：US11610894B2

公开(公告)日：2023-03-21

申请号：US16457657

申请日：2019-06-28

申请人： Intel Corporation

发明人： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Julie Rollins ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Yu-Wen Huang ,  Shu Zhou

IPC分类号： H01L27/108

摘要： Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

公开(公告)号：US20220102271A1

公开(公告)日：2022-03-31

申请号：US17033240

申请日：2020-09-25

申请人： Intel Corporation

发明人： Chieh-Jen Ku ,  Bernhard Sell ,  Pei-Hua Wang

IPC分类号： H01L23/522 ,  H01L27/06 ,  H01L49/02

摘要： Tunable resistance thin film resistors for integrated circuits, related systems, and methods of fabrication are disclosed. Such tunable resistance thin film resistors include electrodes coupled to a resistive thin film that includes a base metal oxide and a second metal element. The resistors are tunable based on the concentration of the second metal element in the composition of the resistive thin film.

公开(公告)号：US11652047B2

公开(公告)日：2023-05-16

申请号：US16457641

申请日：2019-06-28

申请人： Intel Corporation

发明人： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Julie Rollins ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Ting Chen ,  Vinaykumar V. Hadagali

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L27/108

CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L27/1085 ,  H01L27/10805 ,  H01L27/10873

摘要： Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.

公开(公告)号：US20220415896A1

公开(公告)日：2022-12-29

申请号：US17358930

申请日：2021-06-25

申请人： Intel Corporation

发明人： Juan G. Alzate-Vinasco ,  Travis W. LaJoie ,  Wilfred Gomes ,  Fatih Hamzaoglu ,  Pulkit Jain ,  James Waldemer ,  Mark Armstrong ,  Bernhard Sell ,  Pei-Hua Wang ,  Chieh-Jen Ku

IPC分类号： H01L27/108 ,  H01L29/786 ,  H01L29/66

摘要： A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.

公开(公告)号：US11462541B2

公开(公告)日：2022-10-04

申请号：US16222934

申请日：2018-12-17

申请人： Intel Corporation

发明人： Juan G. Alzate Vinasco ,  Abhishek A. Sharma ,  Fatih Hamzaoglu ,  Bernhard Sell ,  Pei-Hua Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Chieh-Jen Ku ,  Travis W. Lajoie ,  Umut Arslan

IPC分类号： H01L21/00 ,  H01L27/108 ,  H01L29/786 ,  H01L49/02 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417

摘要： Embodiments herein describe techniques for a semiconductor device including a substrate oriented in a horizontal direction, and a memory cell including a transistor and a capacitor above the substrate. The transistor includes a gate electrode oriented in a vertical direction substantially orthogonal to the horizontal direction, and a channel layer oriented in the vertical direction, around the gate electrode and separated by a gate dielectric layer from the gate electrode. The capacitor is within an inter-level dielectric layer above the substrate. The capacitor includes a first plate coupled with a second portion of the channel layer of the transistor, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate of the capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.

公开(公告)号：US12080781B2

公开(公告)日：2024-09-03

申请号：US17129867

申请日：2020-12-21

申请人： Intel Corporation

发明人： Noriyuki Sato ,  Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Elliot N. Tan ,  Hui Jae Yoo ,  Travis W. Lajoie ,  Van H. Le ,  Pei-Hua Wang ,  Jason Peck ,  Tobias Brown-Heft

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L27/092

CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L27/0924

摘要： Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed.

公开(公告)号：US11955560B2

公开(公告)日：2024-04-09

申请号：US16914172

申请日：2020-06-26

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Arnab Sen Gupta ,  Travis W. LaJoie ,  Sarah Atanasov ,  Chieh-Jen Ku ,  Bernhard Sell ,  Noriyuki Sato ,  Van Le ,  Matthew Metz ,  Hui Jae Yoo ,  Pei-Hua Wang

IPC分类号： H01L29/66 ,  H01L27/22 ,  H01L29/786 ,  H10B61/00 ,  H10B63/00

CPC分类号： H01L29/7869 ,  H01L29/66969 ,  H10B61/22 ,  H10B63/30

摘要： A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

公开(公告)号：US11929415B2

公开(公告)日：2024-03-12

申请号：US16447880

申请日：2019-06-20

申请人： Intel Corporation

发明人： Chieh-Jen Ku ,  Pei-Hua Wang ,  Bernhard Sell ,  Travis W. Lajoie

IPC分类号： H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H10B12/00

CPC分类号： H01L29/42384 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/66742 ,  H10B12/00 ,  H10B12/01

摘要： A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.

公开(公告)号：US11810980B2

公开(公告)日：2023-11-07

申请号：US16457621

申请日：2019-06-28

申请人： Intel Corporation

发明人： Chieh-Jen Ku ,  Pei-Hua Wang ,  Bernhard Sell ,  Martin M. Mitan ,  Leonard C. Pipes

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L21/768 ,  H01L29/66 ,  H01L27/06

CPC分类号： H01L29/78696 ,  H01L21/76829 ,  H01L27/0688 ,  H01L27/1259 ,  H01L29/6675 ,  H01L29/78618

摘要： Embodiments herein describe techniques for a transistor above a substrate. The transistor includes a channel layer above the substrate. The channel layer includes a first channel material of a first conductivity. In addition, the channel layer further includes elements of one or more additional materials distributed within the channel layer. The channel layer including the elements of the one or more additional materials has a second conductivity different from the first conductivity. Other embodiments may be described and/or claimed.

公开(公告)号：US11784088B2

公开(公告)日：2023-10-10

申请号：US16260632

申请日：2019-01-29

申请人： Intel Corporation

发明人： Chieh-Jen Ku ,  Bernhard Sell ,  Pei-Hua Wang ,  Harish Ganapathy ,  Leonard C. Pipes

IPC分类号： H10B12/00 ,  H01L21/762

CPC分类号： H01L21/76283 ,  H10B12/01 ,  H10B12/20 ,  H10B12/50

摘要： Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.