公开(公告)号：US11652047B2

公开(公告)日：2023-05-16

申请号：US16457641

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Julie Rollins ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Ting Chen ,  Vinaykumar V. Hadagali

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L27/1085 ,  H01L27/10805 ,  H01L27/10873

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.

公开(公告)号：US20230317615A1

公开(公告)日：2023-10-05

申请号：US17708051

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Deepyanti Taneja ,  Travis W. Lajoie ,  Abhishek Anil Sharma ,  Gregory J. George ,  Tarannum Tiasha ,  Huiying Liu ,  Yue Liu ,  Moshe Dolejsi ,  Vinaykumar V. Hadagali ,  Shardul Wadekar ,  Vladimir Nikitin ,  Albert B. Chen ,  Daniel J. Schinke ,  James O'Donnell

IPC: H01L23/532 ,  H01L27/12

CPC classification number: H01L23/53295 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1255 ,  H01L23/5226

Abstract: An integrated circuit includes a first layer, and a second layer above the first layer. A third layer is between a first section of the first layer and a first section of the second layer. A fourth layer is laterally adjacent to the third layer, the fourth layer between a second section of the first layer and a second section of the second layer. In an example, a first dielectric material of the third layer is different (e.g., one or both of compositionally different and structurally different) from a second dielectric material of the fourth layer. In an example, the third and fourth layers are etch stop layers. In some cases, the third and fourth layers are coplanar with each other with respect to their top surfaces, or their bottom surfaces, or both their top and bottom surfaces.