-
公开(公告)号：US12150297B2
公开(公告)日：2024-11-19
申请号：US17129869
申请日：2020-12-21
Applicant: Intel Corporation
Inventor： Noriyuki Sato , Sarah Atanasov , Abhishek A. Sharma , Bernhard Sell , Chieh-Jen Ku , Arnab Sen Gupta , Matthew V. Metz , Elliot N. Tan , Hui Jae Yoo , Travis W. Lajoie , Van H. Le , Pei-Hua Wang
IPC: H10B12/00 , H01L29/786
Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.
-
公开(公告)号：US11610894B2
公开(公告)日：2023-03-21
申请号：US16457657
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Travis W. Lajoie , Abhishek A. Sharma , Van H. Le , Chieh-Jen Ku , Pei-Hua Wang , Jack T. Kavalieros , Bernhard Sell , Tahir Ghani , Gregory George , Akash Garg , Julie Rollins , Allen B. Gardiner , Shem Ogadhoh , Juan G. Alzate Vinasco , Umut Arslan , Fatih Hamzaoglu , Nikhil Mehta , Yu-Wen Huang , Shu Zhou
IPC: H01L27/108
Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.
-
3.发明申请
公开(公告)号：US20220359759A1
公开(公告)日：2022-11-10
申请号：US17308856
申请日：2021-05-05
Applicant: Intel Corporation
Inventor： Chieh-Jen Ku , Andre Baran , Bernhard Sell , David Goldstein , Timothy Jen
IPC: H01L29/786 , H01L29/51 , H01L27/12 , H01L29/66 , H01L21/02
Abstract: Transistors with metal oxide channel material that is in-situ doped for desired charge carrier concentrations. The metal oxide channel material may be deposited by atomic layering of multiple constituent metals with an oxidation of each layer. Such an ALD process may be performed by cyclically depositing a precursor of one of the metals upon a substrate during a deposition phase, and oxidizing the absorbed precursor during an oxidation phase. For a quinary metal oxide, each of three metal precursors may be introduced and oxidized during the ALD process, and charge carrier concentrations may be modulated by further introducing a fourth metal precursor during the ALD process in a manner that disperses this dopant metal within the film at a significantly lower chemical concentration than the other metals.
-
公开(公告)号：US20220102271A1
公开(公告)日：2022-03-31
申请号：US17033240
申请日：2020-09-25
Applicant: Intel Corporation
Inventor： Chieh-Jen Ku , Bernhard Sell , Pei-Hua Wang
IPC: H01L23/522 , H01L27/06 , H01L49/02
Abstract: Tunable resistance thin film resistors for integrated circuits, related systems, and methods of fabrication are disclosed. Such tunable resistance thin film resistors include electrodes coupled to a resistive thin film that includes a base metal oxide and a second metal element. The resistors are tunable based on the concentration of the second metal element in the composition of the resistive thin film.
-
公开(公告)号：US12148734B2
公开(公告)日：2024-11-19
申请号：US17117350
申请日：2020-12-10
Applicant: Intel Corporation
Inventor： Sarah Atanasov , Abhishek A. Sharma , Bernhard Sell , Chieh-Jen Ku , Elliot Tan , Hui Jae Yoo , Noriyuki Sato , Travis W. Lajoie , Van H. Le , Thoe Michaelos
Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.
-
公开(公告)号：US11652047B2
公开(公告)日：2023-05-16
申请号：US16457641
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Travis W. Lajoie , Abhishek A. Sharma , Van H. Le , Chieh-Jen Ku , Pei-Hua Wang , Jack T. Kavalieros , Bernhard Sell , Tahir Ghani , Gregory George , Akash Garg , Julie Rollins , Allen B. Gardiner , Shem Ogadhoh , Juan G. Alzate Vinasco , Umut Arslan , Fatih Hamzaoglu , Nikhil Mehta , Ting Chen , Vinaykumar V. Hadagali
IPC: H01L23/528 , H01L23/522 , H01L27/108
CPC classification number: H01L23/528 , H01L23/5226 , H01L27/1085 , H01L27/10805 , H01L27/10873
Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.
-
公开(公告)号：US20230097793A1
公开(公告)日：2023-03-30
申请号：US17485331
申请日：2021-09-25
Applicant: Intel Corporation
Inventor： Travis W. Lajoie , Pei-hua Wang , Gregory J. George , Bernhard Sell , Juan G. Alzate-Vinasco , Chieh-Jen Ku , Alekhya Nimmagadda
IPC: H01L29/45 , H01L29/24 , H01L29/417 , H01L29/786 , H01L21/02 , H01L21/443 , H01L29/66 , H01L27/108
Abstract: Described herein are integrated circuit devices with lined interconnects. Interconnect liners can help maintain conductivity between semiconductor devices (e.g., transistors) and the interconnects that conduct current to and from the semiconductor devices. In some embodiments, metal interconnects are lined with a tungsten liner. Tungsten liners may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.
-
公开(公告)号：US20220415896A1
公开(公告)日：2022-12-29
申请号：US17358930
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Juan G. Alzate-Vinasco , Travis W. LaJoie , Wilfred Gomes , Fatih Hamzaoglu , Pulkit Jain , James Waldemer , Mark Armstrong , Bernhard Sell , Pei-Hua Wang , Chieh-Jen Ku
IPC: H01L27/108 , H01L29/786 , H01L29/66
Abstract: A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.
-
公开(公告)号：US11462541B2
公开(公告)日：2022-10-04
申请号：US16222934
申请日：2018-12-17
Applicant: Intel Corporation
Inventor： Juan G. Alzate Vinasco , Abhishek A. Sharma , Fatih Hamzaoglu , Bernhard Sell , Pei-Hua Wang , Van H. Le , Jack T. Kavalieros , Tahir Ghani , Chieh-Jen Ku , Travis W. Lajoie , Umut Arslan
IPC: H01L21/00 , H01L27/108 , H01L29/786 , H01L49/02 , H01L29/66 , H01L29/49 , H01L29/417
Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate oriented in a horizontal direction, and a memory cell including a transistor and a capacitor above the substrate. The transistor includes a gate electrode oriented in a vertical direction substantially orthogonal to the horizontal direction, and a channel layer oriented in the vertical direction, around the gate electrode and separated by a gate dielectric layer from the gate electrode. The capacitor is within an inter-level dielectric layer above the substrate. The capacitor includes a first plate coupled with a second portion of the channel layer of the transistor, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate of the capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.
-
公开(公告)号：US20220208770A1
公开(公告)日：2022-06-30
申请号：US17696945
申请日：2022-03-17
Applicant: Intel Corporation
Inventor： Yih Wang , Abhishek A. Sharma , Tahir Ghani , Allen B. Gardiner , Travis W. Lajoie , Pei-hua Wang , Chieh-Jen Ku , Bernhard Sell , Juan G. Alzate-Vinasco , Blake C. Lin
IPC: H01L27/108 , H01L23/522 , H01L23/528 , H01L27/06 , H01L27/12
Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.
