公开(公告)号：US20230253444A1

公开(公告)日：2023-08-10

申请号：US17666745

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Kaan Oguz ,  Chia-Ching Lin ,  I-Cheng Tung ,  Sudarat Lee ,  Sou-Chi Chang ,  Matthew V. Metz ,  Scott B. Clendenning ,  Uygar E. Avci ,  Ian A. Young ,  Jason C. Retasket ,  Edward O. Johnson, JR.

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/65 ,  H01L28/75 ,  H01L27/10829

Abstract: Described herein are capacitor devices formed using perovskite insulators. In one example, a perovskite templating material is formed over an electrode, and a perovskite insulator layer is grown over the templating material. The templating material improves the crystal structure and electrical properties in the perovskite insulator layer. One or both electrodes may be ruthenium. In another example, a perovskite insulator layer is formed between two layers of indium tin oxide (ITO), with the ITO layers forming the capacitor electrodes.

公开(公告)号：US20230253476A1

公开(公告)日：2023-08-10

申请号：US17666627

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Abhishek A. Sharma ,  Matthew V. Metz ,  Kaan Oguz ,  Urusa Shahriar Alaan ,  Scott B. Clendenning ,  Van H. Le ,  Chia-Ching Lin ,  Jason C. Retasket ,  Edward O. Johnson, JR.

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/06 ,  H01L27/108 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/517 ,  H01L29/42392 ,  H01L29/0673 ,  H01L27/10826 ,  H01L29/785 ,  H01L29/4966 ,  H01L29/41775

Abstract: Described herein are transistor devices formed using perovskite gate dielectrics. In one example, a transistor includes a high-k perovskite dielectric material between a gate electrode and a thin film semiconductor channel. In another example, four-terminal transistor includes a semiconductor channel, a gate stack that includes a perovskite dielectric layer on one side of the channel, and a body electrode on an opposite side of the channel. The body electrode adjusts a threshold voltage of the transistor.

公开(公告)号：US20230102219A1

公开(公告)日：2023-03-30

申请号：US17478720

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Matthew V. Metz ,  Hui Jae Yoo ,  Justin R. Weber ,  Van H. Le ,  Jason C. Retasket ,  Abhishek A. Sharma ,  Noriyuki Sato ,  Yu-Jin Chen ,  Eric Mattson ,  Edward O. Johnson, JR.

IPC: H01L29/45 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L27/108 ,  H01L29/417

Abstract: Described herein are integrated circuit devices with metal-oxide semiconductor channels and carbon source and drain (S/D) contacts. S/D contacts conduct current to and from the semiconductor devices, e.g., to the source and drain regions of a transistor. Carbon S/D contacts may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.

公开(公告)号：US20230187553A1

公开(公告)日：2023-06-15

申请号：US17546461

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Gilbert W. Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Scott B. Clendenning ,  Jason C. Retasket ,  Edward O. Johnson, JR.

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L29/78696 ,  H01L29/66742

Abstract: Described herein are integrated circuit devices with source and drain (S/D) contacts with barrier regions. The S/D contacts conduct current to and from semiconductor devices, e.g., to the source and drain regions of a transistor. The barrier regions are formed between the S/D region and an inner conductive structure and reduce the Schottky barrier height between the S/D region and the contact. The barrier regions may include one or more carbon layers and one or more metal layers. A metal layer may include niobium, tantalum, aluminum, or titanium.