公开(公告)号：US20240114692A1

公开(公告)日：2024-04-04

申请号：US17958395

申请日：2022-10-01

申请人： Intel Corporation

发明人： Nazila Haratipour ,  Uygar E. Avci ,  Vachan Kumar ,  Hai Li ,  Yu-Ching Liao ,  Ian Alexander Young

IPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/11502 ,  G11C11/221 ,  G11C11/223 ,  H01L27/1087 ,  H01L29/945

摘要： Inverted pillar capacitors that have a U-shaped insulating layer are oriented with the U-shaped opening of the insulating layer opening toward the surface of the substrate on which the inverted pillar capacitors are formed. The bottom electrodes of adjacent inverted pillar capacitors are isolated from each other by the insulating layers of the adjacent electrodes and the top electrode that fills the volume between the electrodes. By avoiding the need to isolate adjacent bottom electrodes by an isolation dielectric region, inverted pillar capacitors can provide for a greater capacitor density relative to non-inverted pillar capacitors. The insulating layer in inverted pillar capacitors can comprise a ferroelectric material or an antiferroelectric material. The inverted pillar capacitor can be used in memory circuits (e.g., DRAMs) or non-memory applications.

公开(公告)号：US20240105822A1

公开(公告)日：2024-03-28

申请号：US17953648

申请日：2022-09-27

申请人： Intel Corporation

发明人： Kevin P. O'Brien ,  Brandon Holybee ,  Carly Rogan ,  Dmitri Evgenievich Nikonov ,  Punyashloka Debashis ,  Rachel A. Steinhardt ,  Tristan A. Tronic ,  Ian Alexander Young ,  Marko Radosavljevic ,  John J. Plombon

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/775 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66969

摘要： A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.

公开(公告)号：US20230200079A1

公开(公告)日：2023-06-22

申请号：US17555207

申请日：2021-12-17

申请人： Intel Corporation

发明人： Chia-Ching Lin ,  Tanay A. Gosavi ,  Uygar E. Avci ,  Sou-Chi Chang ,  Hai Li ,  Dmitri Evgenievich Nikonov ,  Kaan Oguz ,  Ashish Verma Penumatcha ,  John J. Plombon ,  Ian Alexander Young

IPC分类号： H01L27/11514 ,  H01L49/02 ,  H01L29/51

CPC分类号： H01L27/11514 ,  H01L28/65 ,  H01L29/516

摘要： A first type of ferroelectric capacitor comprises electrodes and an insulating layer comprising ferroelectric oxides. In some embodiments, the electrodes and the insulating layer comprise perovskite ferroelectric oxides. A second type of ferroelectric capacitor comprises a ferroelectric insulating layer comprising certain monochalcogenides. Both types of ferroelectric capacitors can have a coercive voltage that is less than one volt. Such capacitors are attractive for use in low-voltage non-volatile embedded memories for next-generation semiconductor manufacturing technologies.

公开(公告)号：US20230058938A1

公开(公告)日：2023-02-23

申请号：US17409483

申请日：2021-08-23

申请人： Intel Corporation

发明人： Punyashloka Debashis ,  Dmitri Evgenievich Nikonov ,  Hai Li ,  Chia-Ching Lin ,  Raseong Kim ,  Tanay A. Gosavi ,  Ashish Verma Penumatcha ,  Uygar E. Avci ,  Marko Radosavljevic ,  Ian Alexander Young

IPC分类号： G11C11/22 ,  H01L27/1159

摘要： A pbit device, in one embodiment, includes a first field-effect transistor (FET) that includes a source region, a drain region, a source electrode on the source region, a drain electrode on the drain region, a channel region between the source and drain regions, a dielectric layer on a surface over the channel region, an electrode layer above the dielectric layer, and a ferroelectric (FE) material layer between the dielectric layer and the electrode layer. The pbit device also includes a second FET comprising a source electrode, a drain electrode, and a gate electrode. The drain electrode of the second FET is connected to the drain electrode of the first FET.

公开(公告)号：US20230284538A1

公开(公告)日：2023-09-07

申请号：US17685053

申请日：2022-03-02

申请人： Intel Corporation

发明人： Punyashloka Debashis ,  Chia-Ching Lin ,  Hai Li ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC分类号： H01L43/06 ,  H01L27/22 ,  H01L43/14 ,  H01F10/32 ,  G11C11/18 ,  G11C11/16 ,  H03K19/18

CPC分类号： H01L43/06 ,  H01L27/228 ,  H01L43/14 ,  H01F10/3286 ,  H01F10/3268 ,  G11C11/18 ,  G11C11/1673 ,  G11C11/1675 ,  H03K19/18 ,  H01L43/10

摘要： A spin orbit logic device includes: a first electrically conductive layer; a layer including a magnetoelectric material (ME layer) on the first electrically conductive layer; a layer including a ferromagnetic material with in-plane magnetic anisotropy (FM layer) on the ME layer; a second electrically conductive layer on the FM layer; a layer including a dielectric material on the second electrically conductive layer (coupling layer); a layer including a spin orbit coupling material (SOC layer) on the coupling layer; and a layer including a ferromagnetic material with perpendicular magnetic anisotropy (PMA layer) on the SOC layer.

公开(公告)号：US20230077177A1

公开(公告)日：2023-03-09

申请号：US17469320

申请日：2021-09-08

申请人： Intel Corporation

发明人： Hai Li ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Tanay A. Gosavi ,  Ian Alexander Young

IPC分类号： H01L27/22 ,  H01L43/06 ,  H01L43/10 ,  H01L25/10

摘要： A spin orbit logic (SOL) device includes a first electrically conductive layer; a layer comprising a ferroelectric material (FE layer) on the first electrically conductive layer; a second electrically conductive layer on the FE layer; and a spin orbit coupling (SOC) stack including a first layer (SOC1 layer) including a first SOC material, and a second layer (SOC2 layer) including a second SOC material, the SOC1 layer adjacent the FE layer.

公开(公告)号：US20230070486A1

公开(公告)日：2023-03-09

申请号：US17467124

申请日：2021-09-03

申请人： Intel Corporation

发明人： Punyashloka Debashis ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Hai Li

IPC分类号： G11C11/16 ,  G06F7/58 ,  G06F17/16

摘要： Technologies for non-uniform random number generation are disclosed. In one embodiment, the distribution of resistance of a magnetic tunnel junction (MTJ) can be controlled by applying a mechanical strain with a piezoelectric layer and by applying a spin torque by a spin-orbit torque layer. The distribution of resistance can be approximately a Gaussian distribution. In another embodiment, an array of N probabilistic bits (p-bits) has a bias and feedback matrix that result in the array of p-bits outputting an N-bit random number with a non-uniform distribution, such as a Gaussian distribution.

公开(公告)号：US20230068950A1

公开(公告)日：2023-03-02

申请号：US17405953

申请日：2021-08-18

申请人： Intel Corporation

发明人： Dmitri Evgenievich Nikonov ,  Hai Li ,  Ian Alexander Young

IPC分类号： H01L29/78 ,  H01L29/10 ,  H03K19/00

摘要： A leakage insensitive transistor includes a substrate, a source region, a drain region, a channel region between the source region and drain region, a gate dielectric on the channel region, first and second electrodes on the gate dielectric, and third and fourth electrodes on the substrate. The leakage insensitive transistor may be operated by applying a first logic signal to the first electrode, floating the second electrode of the FET, applying a second logic signal opposite the first logic signal to the third electrode, and floating the fourth electrode. A logic circuit may include multiple leakage insensitive transistors.

公开(公告)号：US20240222506A1

公开(公告)日：2024-07-04

申请号：US18148871

申请日：2022-12-30

申请人： Intel Corporation

发明人： Hojoon Ryu ,  Punyashloka Debashis ,  Rachel A. Steinhardt ,  Kevin P. O'Brien ,  John J. Plombon ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/8256 ,  H01L27/092 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76

CPC分类号： H01L29/78391 ,  H01L21/02568 ,  H01L21/8256 ,  H01L27/092 ,  H01L29/24 ,  H01L29/516 ,  H01L29/66969 ,  H01L29/7606

摘要： An apparatus, comprising a field effect transistor comprising a ferroelectric material, a channel material comprising a transition metal and a chalcogen, a source and a drain coupled to the channel material, the source and drain comprising a conductive material.

公开(公告)号：US20240206348A1

公开(公告)日：2024-06-20

申请号：US18083493

申请日：2022-12-17

申请人： Intel Corporation

发明人： Punyashloka Debashis ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Hai Li

IPC分类号： H10N52/85 ,  G11C11/16 ,  H03K19/20 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85

CPC分类号： H10N52/85 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H03K19/20 ,  H10B61/22 ,  H10N50/10 ,  H10N50/85

摘要： In embodiments herein, probabilistic and deterministic logic devices include reduced symmetry materials, such as two-dimensional (2D) transition metal dichalcogenide (TMD) materials (e.g., NbSe2 or MoTe2).