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1.发明公开公开(公告)号：US20230155550A1
公开(公告)日：2023-05-18
申请号：US17530250
申请日：2021-11-18
申请人： Intel Corporation
发明人： Gary A. Allen , Tanay A. Gosavi , Raseong Kim , Dmitri Evgenievich Nikonov , Ian Alexander Young
摘要： In one embodiment, a piezo-resistive resonator device includes one or more drive transistors with source and drain regions in a first well and a sense transistor with source and drain regions in a second well of opposite polarity than the first well. The gates of the drive and sense transistor are connected to a first direct current (DC) source. The drain region of the sense transistor is connected to a second DC source, and the source and drain regions of the drive transistor are connected to an alternating current (AC) source.
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公开(公告)号：US20230189659A1
公开(公告)日：2023-06-15
申请号：US17550663
申请日：2021-12-14
申请人： Intel Corporation
发明人： Punyashloka Debashis , Tanay A. Gosavi , Hai Li , Chia-Ching Lin , Dmitri Evgenievich Nikonov , Kaan Oguz , Ashish Verma Penumatcha , Marko Radosavljevic , Ian Alexander Young
摘要： A probabilistic bit (p-bit) comprises a magnetic tunnel junction (MTJ) comprising a free layer whose magnetization orientation randomly fluctuates in the presence of thermal noise. The p-bit MTJ comprises a reference layer, a free layer, and an insulating layer between the reference and free layers. The reference layer and the free layer comprise synthetic antiferromagnets. The use of a synthetic antiferromagnet for the reference layer reduces the amount of stray magnetic field that can impact the magnetization of the free layer and the use of a synthetic antiferromagnet for the free layer reduces stray magnetic field bias on p-bit random number generation. Tuning the thickness of the nonmagnetic layer of synthetic antiferromagnet free layer can result in faster random number generation time relative to a comparable MTJ with a free layer comprising a single-layer ferromagnet.
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公开(公告)号：US20230065198A1
公开(公告)日：2023-03-02
申请号：US17465752
申请日：2021-09-02
申请人： Intel Corporation
发明人： Ian Alexander Young , Dmitri Evgenievich Nikonov , Chia-Ching Lin , Tanay A. Gosavi , Ashish Verma Penumatcha , Kaan Oguz , Punyashloka Debashis
IPC分类号： H01L43/04 , H01L27/22 , H01L43/02 , H01L43/06 , H01L43/10 , G11C11/16 , G11C11/18 , H01F10/32
摘要： A memory device, an integrated circuit component including an array of the memory devices, and an integrated device assembly including the integrated circuit component. The memory devices includes a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material. The memory device may correspond to a magnetic tunnel junction (MTJ) magnetic random access memory bit cell, and the memory stack may correspond to a MTJ device.
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公开(公告)号：US20230077177A1
公开(公告)日：2023-03-09
申请号：US17469320
申请日：2021-09-08
申请人： Intel Corporation
摘要： A spin orbit logic (SOL) device includes a first electrically conductive layer; a layer comprising a ferroelectric material (FE layer) on the first electrically conductive layer; a second electrically conductive layer on the FE layer; and a spin orbit coupling (SOC) stack including a first layer (SOC1 layer) including a first SOC material, and a second layer (SOC2 layer) including a second SOC material, the SOC1 layer adjacent the FE layer.
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公开(公告)号：US20230086080A1
公开(公告)日：2023-03-23
申请号：US17482131
申请日：2021-09-22
申请人： Intel Corporation
发明人： Chia-Ching Lin , Dmitri Evgenievich Nikonov , Ian Alexander Young , John J. Plombon , Hai Li , Kaan Oguz , Tanay A. Gosavi , Emily Walker
摘要： In one embodiment, an apparatus includes a magnet, a first structure, and a second structure. The first structure includes a first conductive trace and a magnetoelectric material. The first conductive trace is coupled to an input voltage terminal, and the magnetoelectric material is coupled to the first conductive trace and the magnet. The second structure includes a superlattice structure and a second conductive trace. The superlattice structure includes one or more topological insulator materials. Moreover, the superlattice structure is coupled to the magnet and the second conductive trace, and the second conductive trace is coupled to an output voltage terminal.
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公开(公告)号：US20230200079A1
公开(公告)日：2023-06-22
申请号：US17555207
申请日：2021-12-17
申请人： Intel Corporation
发明人： Chia-Ching Lin , Tanay A. Gosavi , Uygar E. Avci , Sou-Chi Chang , Hai Li , Dmitri Evgenievich Nikonov , Kaan Oguz , Ashish Verma Penumatcha , John J. Plombon , Ian Alexander Young
IPC分类号： H01L27/11514 , H01L49/02 , H01L29/51
CPC分类号： H01L27/11514 , H01L28/65 , H01L29/516
摘要： A first type of ferroelectric capacitor comprises electrodes and an insulating layer comprising ferroelectric oxides. In some embodiments, the electrodes and the insulating layer comprise perovskite ferroelectric oxides. A second type of ferroelectric capacitor comprises a ferroelectric insulating layer comprising certain monochalcogenides. Both types of ferroelectric capacitors can have a coercive voltage that is less than one volt. Such capacitors are attractive for use in low-voltage non-volatile embedded memories for next-generation semiconductor manufacturing technologies.
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公开(公告)号：US20230058938A1
公开(公告)日：2023-02-23
申请号：US17409483
申请日：2021-08-23
申请人： Intel Corporation
发明人： Punyashloka Debashis , Dmitri Evgenievich Nikonov , Hai Li , Chia-Ching Lin , Raseong Kim , Tanay A. Gosavi , Ashish Verma Penumatcha , Uygar E. Avci , Marko Radosavljevic , Ian Alexander Young
IPC分类号： G11C11/22 , H01L27/1159
摘要： A pbit device, in one embodiment, includes a first field-effect transistor (FET) that includes a source region, a drain region, a source electrode on the source region, a drain electrode on the drain region, a channel region between the source and drain regions, a dielectric layer on a surface over the channel region, an electrode layer above the dielectric layer, and a ferroelectric (FE) material layer between the dielectric layer and the electrode layer. The pbit device also includes a second FET comprising a source electrode, a drain electrode, and a gate electrode. The drain electrode of the second FET is connected to the drain electrode of the first FET.
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