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公开(公告)号：US20200098654A1
公开(公告)日：2020-03-26
申请号：US16136274
申请日：2018-09-20
发明人： Tsang-Po Yang , Jui-Hsiu Jao , Chun-Shun Huang
IPC分类号： H01L21/66 , H01L29/78 , H01L23/60 , H01L23/522
摘要： A method includes forming a transistor over a substrate; forming a conductive structure over the substrate, such that a first end of the conductive structure is electrically coupled to a gate of the transistor, and a second end of the conductive structure is electrically coupled to the substrate; applying biases to the gate of the transistor and source/drain structures of the transistor; determining whether the first end and the second end of the conductive structure are electrically connected; generating, based on the determination, a first result indicating that the first end and the second end of the conductive structure are electrically connected; and qualifying the conductive structure as an antenna in response to the first result.
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公开(公告)号：US11843030B2
公开(公告)日：2023-12-12
申请号：US17691264
申请日：2022-03-10
发明人： Yi-Ju Chen , Jui-Hsiu Jao
IPC分类号： H01L29/78 , H01L29/06 , G11C11/407
CPC分类号： H01L29/0653 , G11C11/407 , H01L29/78
摘要： A fuse element, a semiconductor device, and a method for activating a backup unit are provided. The fuse element includes an active area, which includes a source region and a drain region beside the source region, a gate region disposed on the active area, and a shallow trench isolation (STI) structure surrounding the active area. In addition, the drain region includes a terminal configured to receive a stress voltage, such that a conductive path is established through the drain region to the source region.
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公开(公告)号：US11456224B2
公开(公告)日：2022-09-27
申请号：US16990654
申请日：2020-08-11
发明人： Tsang-Po Yang , Jui-Hsiu Jao
IPC分类号： H01L21/66 , H01L27/108
摘要： The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a semiconductor substrate, a memory device and a test structure. The memory device is disposed on the semiconductor substrate, and includes a device area and an edge area. The edge area surrounds the device area. The test structure is disposed on the semiconductor substrate, and includes a dummy area, a test edge area and a plurality of unit cells. The test edge area surrounds the dummy area. The unit cells have a first group disposed in the dummy area and a second group disposed in the test edge area. The second group of unit cells includes the outermost unit cells of the plurality of unit cells. A shape surrounded by the edge area in a top view is different from a shape surrounded by the test edge area in the top view.
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公开(公告)号：US11262398B2
公开(公告)日：2022-03-01
申请号：US16670134
申请日：2019-10-31
发明人： Ching-Chung Wang , Jui-Hsiu Jao
摘要： The present disclosure provides a testing fixture. The testing fixture includes a carrier, a plurality of sets of electrical lines and a plurality of electrical lines. The carrier includes a base and a frame extending along an upper surface of the base. The base and the frame define a first recess, a second recess extending longitudinally from the first recess, and a third recess extending transversely from the first recess. The plurality of sets of electrical contacts are disposed on the base and arranged in a rotationally symmetrical manner, and the electrical lines are electrically connected to the plurality of sets of electrical contacts.
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公开(公告)号：US11668745B1
公开(公告)日：2023-06-06
申请号：US17690133
申请日：2022-03-09
发明人： Yi-Ju Chen , Jui-Hsiu Jao
CPC分类号： G01R31/2887 , G01R31/2891
摘要： A probe apparatus and a wafer inspection method are provided. The probe apparatus includes a chuck configured to support a wafer, a track surrounding the chuck, a tester disposed on the track and having a probe, and a processing unit in communication with the tester and configured to move the tester circumferentially around the wafer such that the probe is moved from a first portion on the wafer to a second portion on the wafer.
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公开(公告)号：US11024553B2
公开(公告)日：2021-06-01
申请号：US17031870
申请日：2020-09-24
发明人： Tsang-Po Yang , Jui-Hsiu Jao , Chun-Shun Huang
IPC分类号： H01L29/78 , H01L21/66 , H01L23/60 , H01L23/522
摘要： A method includes forming a transistor over a substrate; forming a conductive structure over the substrate, such that a first end of the conductive structure is electrically coupled to a gate of the transistor, and a second end of the conductive structure is electrically coupled to the substrate; applying biases to the gate of the transistor and source/drain structures of the transistor; determining whether the first end and the second end of the conductive structure are electrically connected; generating, based on the determination, a first result indicating that the first end and the second end of the conductive structure are electrically connected; and qualifiying the conductive structure as an antenna in response to the first result.
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公开(公告)号：US10985077B2
公开(公告)日：2021-04-20
申请号：US16459017
申请日：2019-07-01
发明人： Chun-Shun Huang , Jui-Hsiu Jao , Wei-Li Lai
IPC分类号： H01L21/8238 , H01L21/66
摘要： The present disclosure provides a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate, a first type region, and a second type region. The first type region is disposed on the substrate and has a ring structure. The second type region is disposed on the substrate and disposed in the center of the first type region. The second type region has a square shape and includes a plurality of corners.
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公开(公告)号：US10825744B2
公开(公告)日：2020-11-03
申请号：US16136274
申请日：2018-09-20
发明人： Tsang-Po Yang , Jui-Hsiu Jao , Chun-Shun Huang
IPC分类号： H01L29/78 , H01L21/66 , H01L23/60 , H01L23/522
摘要： A method includes forming a transistor over a substrate; forming a conductive structure over the substrate, such that a first end of the conductive structure is electrically coupled to a gate of the transistor, and a second end of the conductive structure is electrically coupled to the substrate; applying biases to the gate of the transistor and source/drain structures of the transistor; determining whether the first end and the second end of the conductive structure are electrically connected; generating, based on the determination, a first result indicating that the first end and the second end of the conductive structure are electrically connected; and qualifying the conductive structure as an antenna in response to the first result.
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公开(公告)号：US10756693B1
公开(公告)日：2020-08-25
申请号：US16596749
申请日：2019-10-08
发明人： Kai-Po Shang , Jui-Hsiu Jao
摘要： An integrated circuit device is disclosed. The integrated circuit device includes a capacitor array, a decoder circuit, and an integrated circuit. The capacitor array includes a plurality of capacitor units. The decoder circuit is coupled to the capacitor array. The integrated circuit is coupled to the decoder circuit. The decoder circuit is configured to conduct part of the plurality of capacitor units, and to un-conduct part of the plurality of capacitor units, so as to adjust a capacitance value coupled to the integrated circuit.
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公开(公告)号：US10720389B2
公开(公告)日：2020-07-21
申请号：US15802085
申请日：2017-11-02
发明人： Chih-Ying Chang , Jui-Hsiu Jao
IPC分类号： H01L23/525
摘要： An anti-fuse structure includes an active area, a gate electrode over the active area, and a dielectric layer between the active area and the gate electrode. The active area and the gate electrode partially overlap in a vertical projection direction, forming a plurality of channels. One of the gate electrode and the active area includes a plurality of extending portions to form the plurality of channels.
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