Invention Publication
- Patent Title: SOURCE AND DRAIN CONTACTS FORMED USING SACRIFICIAL REGIONS OF SOURCE AND DRAIN
-
Application No.: US17838646Application Date: 2022-06-13
-
Publication No.: US20230402513A1Publication Date: 2023-12-14
- Inventor: Rohit Galatage , Willy Rachmady , Subrina Rafique , Nitesh Kumar , Cheng-Ying Huang , Jami A. Wiedemer , Nicloe K. Thomas , Munzarin F. Qayyum , Patrick Morrow , Marko Radosavljevic , Mauro J. Kobrinsky
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L27/092 ; H01L29/06 ; H01L29/423 ; H01L29/417 ; H01L29/786 ; H01L29/775 ; H01L21/02 ; H01L21/822 ; H01L21/8238 ; H01L29/66

Abstract:
An integrated circuit structure includes a device including a source region, a drain region, a body laterally between the source and drain regions, and a source contact coupled to the source region. In an example, the source region includes a first region, and a second region compositionally different from and above the first region. The source contact extends through the second region and extends within the first region. In an example where the device is a p-channel metal-oxide-semiconductor (PMOS) device, a concentration of germanium within the second region is different (e.g., higher) than a concentration of germanium within the first region. In another example where the device is a n-channel metal-oxide-semiconductor (NMOS) device, a doping concentration level of a dopant (e.g., an n-type dopant) within the second region is different (e.g., higher) from a doping concentration level of the dopant within the first region.
Information query
IPC分类: