Invention Publication
- Patent Title: 3D SOURCE AND DRAIN CONTACTS TUNED FOR PMOS AND NMOS
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Application No.: US17833045Application Date: 2022-06-06
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Publication No.: US20230395717A1Publication Date: 2023-12-07
- Inventor: Willy Rachmady , Nitesh Kumar , Jami A. Wiedemer , Cheng-Ying Huang , Marko Radosavljevic , Mauro J. Kobrinsky , Patrick Morrow , Rohit Galatage , David N. Goldstein , Christopher J. Jezewski
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/423 ; H01L29/06 ; H01L29/45 ; H01L27/092
Abstract:
An integrated circuit structure includes a first device, and a second device laterally adjacent to the first device. The first device includes (i) a first source region, and a first source contact including a first conductive material, (ii) a first drain region, and a first drain contact including the first conductive material, and (iii) a first body laterally between the first source region and the first drain region. The second device includes (i) a second source region, and a second source contact including a second conductive material, (ii) a second drain region, and a second drain contact including the second conductive material, and (iii) a second body laterally between the second source region and the second drain region. The first and second conductive materials are compositionally different. The first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.
Information query
IPC分类:
