知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.012 seconds)

    Nitrogen controlled growth of dislocation loop in stress enhanced transistor
    2.
    发明授权
    Nitrogen controlled growth of dislocation loop in stress enhanced transistor 有权
    应力增强晶体管中位错环的氮控制生长

    公开(公告)号：US07226824B2

    公开(公告)日：2007-06-05

    申请号：US10918818

    申请日：2004-08-13

    Applicant: Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    Inventor： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    IPC: H01L21/338

    CPC classification number: H01L29/7842 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/7833

    Abstract: Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

    Abstract translation: 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

    DIFFUSED TIP EXTENSION TRANSISTOR
    3.
    发明申请
    DIFFUSED TIP EXTENSION TRANSISTOR 审中-公开
    扩展尖端延伸晶体管

    公开(公告)号：US20160380102A1

    公开(公告)日：2016-12-29

    申请号：US15038969

    申请日：2013-12-27

    Applicant: Pratik PATEL ,  Jami A. WIEDEMER ,  Paul A. PACKAN ,  INTEL CORPORATION

    Inventor： Pratik A. PATEL ,  Mark Y. LIU ,  Jami A. WIEDEMER ,  Paul A. PACKAN

    IPC: H01L29/78 ,  H01L29/24 ,  H01L21/225 ,  H01L29/66 ,  H01L21/324 ,  H01L29/08 ,  H01L29/267

    CPC classification number: H01L29/7848 ,  H01L21/2253 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66492 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

    Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

    Abstract translation: 一种方法，包括在鳍片的接合区域中形成开口并在基底上延伸的方法; 在开口中引入掺杂的半导体材料; 并对掺杂的半导体材料进行热处理。 一种方法，包括在从衬底延伸的翅片上形成栅电极; 在所述鳍片的邻近所述栅电极的相对侧上形成开口; 在开口中引入掺杂的半导体材料; 并且热处理足以引起掺杂半导体材料中的掺杂剂扩散的掺杂​​半导体材料。 一种装置，包括横跨从基板延伸的翅片的栅电极; 以及半导体材料填充的开口，在栅电极的相邻相邻两侧的接合区域中，其中半导体材料包括掺杂剂。

    Low damage doping technique for self-aligned source and drain regions
    4.
    发明授权
    Low damage doping technique for self-aligned source and drain regions 失效
    用于自对准源极和漏极区域的低损耗掺杂技术

    公开(公告)号：US5976939A

    公开(公告)日：1999-11-02

    申请号：US498028

    申请日：1995-07-03

    Applicant: Scott Thompson ,  Mark T. Bohr ,  Paul A. Packan

    Inventor： Scott Thompson ,  Mark T. Bohr ,  Paul A. Packan

    IPC: H01L21/225 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092

    CPC classification number: H01L29/6659 ,  H01L21/2257 ,  H01L21/823814 ,  H01L29/6656

    Abstract: A process for fabricating a source and drain region which includes a more lightly doped source and drain tip region immediately adjacent to the gate and a more heavily doped main portion of the source and drain region spaced apart from the gate. A first layer of glass (2% BSG) is used to provide the source of doping for the tip region and a second layer of glass (6% BSG) is used to provide the dopant for the more heavily doped major portion of source and drain regions. Spacers are formed between the glass layers to define the tip region from the main portion of the source and drain regions.

    Abstract translation: 一种用于制造源极和漏极区的工艺，其包括与栅极紧邻的更轻掺杂的源极和漏极尖端区域以及与栅极间隔开的源极和漏极区域的更重掺杂的主要部分。 使用第一层玻璃（2％BSG）为尖端区域提供掺杂源，并且使用第二层玻璃（6％BSG）为源和漏极的更重掺杂的主要部分提供掺杂剂 地区。 间隔件形成在玻璃层之间，以限定源区和漏区的主要部分的尖端区域。

    Nitrogen controlled growth of dislocation loop in stress enhanced transistor
    9.
    发明授权
    Nitrogen controlled growth of dislocation loop in stress enhanced transistor 有权
    应力增强晶体管中位错环的氮控制生长

    公开(公告)号：US06800887B1

    公开(公告)日：2004-10-05

    申请号：US10405110

    申请日：2003-03-31

    Applicant: Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    Inventor： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    IPC: H01L2980

    CPC classification number: H01L29/7842 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/7833

    Abstract: Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

    Abstract translation: 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

Patent Agency Ranking