公开(公告)号：US20230317729A1

公开(公告)日：2023-10-05

申请号：US17710584

申请日：2022-03-31

申请人： Intel Corporation

发明人： Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Hai Li ,  Ian Alexander Young ,  Julien Sebot ,  Punyashloka Debashis

IPC分类号： H01L27/118 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L27/11803 ,  H01L29/78391 ,  H01L29/66984

摘要： In one embodiment, an integrated circuit apparatus includes a plurality of metallization layers, each metallization layer comprising voltage supply lines and signal lines. The apparatus also includes logic circuits formed between respective pairs of metallization layers, with each logic circuit comprising non-CMOS logic devices to perform an operation on a respective bit of an input set of bits. The non-CMOS logic devices may include one or more of ferroelectric field-effect transistor (FeFET) devices or spintronic logic devices (e.g., magnetoelectric spin orbit (MESO) devices or ferroelectric spin orbit logic (FSOL) devices), and each logic circuit may be formed on a different vertical plane within the apparatus.

公开(公告)号：US20230187407A1

公开(公告)日：2023-06-15

申请号：US17548304

申请日：2021-12-10

申请人： Intel Corporation

发明人： Carleton L. Molnar ,  Adel A. Elsherbini ,  Tanay Karnik ,  Shawna M. Liff ,  Robert J. Munoz ,  Julien Sebot ,  Johanna M. Swan ,  Nevine Nassif ,  Gerald S. Pasdast ,  Krishna Bharath ,  Neelam Chandwani ,  Dmitri E. Nikonov

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L25/0652 ,  H01L23/481 ,  H01L24/08 ,  H01L24/20 ,  H01L2224/2101 ,  H01L2224/08147 ,  H01L2924/37001 ,  H01L2924/1427

摘要： A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.

公开(公告)号：US20220415743A1

公开(公告)日：2022-12-29

申请号：US17358361

申请日：2021-06-25

申请人： Intel Corporation

发明人： Feras Eid ,  Adel Elsherbini ,  Johanna Swan ,  Shawna Liff ,  Aleksandar Aleksov ,  Julien Sebot

IPC分类号： H01L23/36 ,  H01L25/065 ,  H01L21/50 ,  H01L27/06 ,  H01L23/00

摘要： Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.

公开(公告)号：US09170815B2

公开(公告)日：2015-10-27

申请号：US13752916

申请日：2013-01-29

申请人： Intel Corporation

发明人： Yen-Kuang Chen ,  William W. Macy, Jr. ,  Matthew Holliman ,  Eric L. Debes ,  Minerva M. Yeung ,  Huy V. Nguyen ,  Julien Sebot

IPC分类号： G06F5/01 ,  G06F9/30 ,  G06F9/38 ,  G06F17/14 ,  G06F17/15 ,  G06F15/80

CPC分类号： G06F9/30145 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3816 ,  G06F9/3885 ,  G06F15/8007 ,  G06F17/147 ,  G06F17/15

摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

公开(公告)号：US20220415853A1

公开(公告)日：2022-12-29

申请号：US17358948

申请日：2021-06-25

申请人： Intel Corporation

发明人： Aleksandar Aleksov ,  Johanna Swan ,  Shawna Liff ,  Feras Eid ,  Adel Elsherbini ,  Julien Sebot

IPC分类号： H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

摘要： A composite integrated circuit (IC) structure includes at least a first IC die in a stack with a second IC die. Each die has a device layer and metallization layers interconnected to transistors of the device layer and terminating at features. First features of the first IC die are primarily of a first composition with a first microstructure. Second features of the second IC die are primarily of a second composition or a second microstructure. A first one of the second features is in direct contact with one of the first features. The second composition has a thermal conductivity at least an order of magnitude lower than that of the first composition and first microstructure. The first composition may have a thermal conductivity at least 40 times that of the second composition or second microstructure.

公开(公告)号：US20190220280A1

公开(公告)日：2019-07-18

申请号：US16208534

申请日：2018-12-03

申请人： Intel Corporation

发明人： Julien Sebot ,  William W. Macy, JR. ,  Eric L. Debes ,  Huy V. Nguyen

IPC分类号： G06F9/30 ,  G06F15/80 ,  G06F17/15 ,  G06F17/14 ,  G06F9/38

CPC分类号： G06F9/30145 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3816 ,  G06F9/3885 ,  G06F15/8007 ,  G06F17/147 ,  G06F17/15

摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

公开(公告)号：US09218184B2

公开(公告)日：2015-12-22

申请号：US13843521

申请日：2013-03-15

申请人： INTEL CORPORATION

发明人： Julien Sebot ,  William W. Macy, Jr. ,  Eric L. Debes ,  Huy V. Nguyen

IPC分类号： G06F15/00 ,  G06F15/76 ,  G06F9/30 ,  G06F9/38 ,  G06F17/14 ,  G06F17/15 ,  G06F15/80

CPC分类号： G06F9/30145 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3816 ,  G06F9/3885 ,  G06F15/8007 ,  G06F17/147 ,  G06F17/15

摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

摘要翻译： 用于使用SIMD合并指令执行比特流缓冲器操作的方法，装置和程序装置。 一个实施例的方法包括确定在第一数据块中是否存在用于部分可变长度符号的任何未处理的数据比特。 执行移位合并操作以将来自第一数据块的未处理数据位与第二数据块合并。 形成合并的数据块。 从合并的数据块中提取由未处理的数据位和来自第二数据块的多个数据位组成的合并的可变长度符号。

公开(公告)号：US20230315192A1

公开(公告)日：2023-10-05

申请号：US18296560

申请日：2023-04-06

申请人： Intel Corporation

发明人： Rolf Kuehnis ,  Matthew Long ,  Julien Sebot

IPC分类号： G06F1/3296 ,  G01K7/02 ,  H03K17/082

CPC分类号： G06F1/3296 ,  G01K7/021 ,  H03K17/082

摘要： In one embodiment, a processor includes: a first plurality of intellectual property (IP) circuits to execute operations; and a second plurality of integrated voltage regulators, where the second plurality of integrated voltage regulators are oversubscribed with respect to the first plurality of IP circuits. Other embodiments are described and claimed.

公开(公告)号：US20230284457A1

公开(公告)日：2023-09-07

申请号：US17688495

申请日：2022-03-07

申请人： Intel Corporation

发明人： Hai Li ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Punyashloka Debashis ,  Ian Alexander Young ,  Julien Sebot

IPC分类号： H01L27/22 ,  H01L43/04 ,  H01L43/06

CPC分类号： H01L27/22 ,  H01L43/04 ,  H01L43/06

摘要： In one embodiment, a first integrated circuit component, a second integrated circuit component, and an electrical interconnect coupling the first integrated circuit component and the second integrated circuit component. The interconnect comprises one or more spintronic logic devices.

公开(公告)号：US09189238B2

公开(公告)日：2015-11-17

申请号：US13752987

申请日：2013-01-29

申请人： Intel Corporation

发明人： Yen-Kuang Chen ,  William W. Macy, Jr. ,  Matthew Holliman ,  Eric L. Debes ,  Minerva M. Yeung ,  Huy V. Nguyen ,  Julien Sebot

IPC分类号： G06F5/01 ,  G06F9/30 ,  G06F9/38 ,  G06F17/14 ,  G06F17/15 ,  G06F15/80

CPC分类号： G06F9/30145 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3816 ,  G06F9/3885 ,  G06F15/8007 ,  G06F17/147 ,  G06F17/15

摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.