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公开(公告)号：US09170815B2
公开(公告)日：2015-10-27
申请号：US13752916
申请日：2013-01-29
Applicant: Intel Corporation
Inventor： Yen-Kuang Chen , William W. Macy, Jr. , Matthew Holliman , Eric L. Debes , Minerva M. Yeung , Huy V. Nguyen , Julien Sebot
CPC classification number: G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
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公开(公告)号：US10152323B2
公开(公告)日：2018-12-11
申请号：US15299914
申请日：2016-10-21
Applicant: Intel Corporation
Inventor： Patrice L. Roussel , William W. Macy, Jr. , Huy V. Nguyen , Eric L. Debes
Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.
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公开(公告)号：US10146541B2
公开(公告)日：2018-12-04
申请号：US14939932
申请日：2015-11-12
Applicant: INTEL CORPORATION
Inventor： Julien Sebot , William W. Macy, Jr. , Eric L. Debes , Huy V. Nguyen
Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
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公开(公告)号：US20150154023A1
公开(公告)日：2015-06-04
申请号：US14586581
申请日：2014-12-30
Applicant: INTEL CORPORATION
Inventor： William W. Macy, JR. , Eric L. Debes , Patrice L. Roussel , Huy V. Nguyen
IPC: G06F9/30
CPC classification number: G06F9/30032 , G06F7/76 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30098 , G06F9/30105 , G06F9/30109 , G06F9/3012 , G06F9/3013 , G06F9/30145 , G06F9/3802 , G06F9/3885 , G06F9/3887
Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.
Abstract translation: 用于混洗数据的方法，装置和程序装置。 一个实施例的方法包括接收具有一组L个数据元素的第一操作数和具有一组L个控制元素的第二操作数。 对于每个控制元件，如果没有设置其齐平零场并将零置于相关联的结果数据元素位置中，则由单独控制元件指定的来自第一操作数数据元素的数据被混洗到相关联的合成数据元素位置 没有设置齐平零场。
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公开(公告)号：US10474466B2
公开(公告)日：2019-11-12
申请号：US15856947
申请日：2017-12-28
Applicant: Intel Corporation
Inventor： William W. Macy, Jr. , Huy V. Nguyen
Abstract: Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second block are corrected.
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Patent Agency Ranking
公开(公告)号：US20190220280A1
公开(公告)日：2019-07-18
申请号：US16208534
申请日：2018-12-03
Applicant: Intel Corporation
Inventor： Julien Sebot , William W. Macy, JR. , Eric L. Debes , Huy V. Nguyen
CPC classification number: G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
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公开(公告)号：US09229719B2
公开(公告)日：2016-01-05
申请号：US14586581
申请日：2014-12-30
Applicant: Intel Corporation
Inventor： William W. Macy, Jr. , Eric L. Debes , Patrice L. Roussel , Huy V. Nguyen
CPC classification number: G06F9/30032 , G06F7/76 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30098 , G06F9/30105 , G06F9/30109 , G06F9/3012 , G06F9/3013 , G06F9/30145 , G06F9/3802 , G06F9/3885 , G06F9/3887
Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.
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公开(公告)号：US09218184B2
公开(公告)日：2015-12-22
申请号：US13843521
申请日：2013-03-15
Applicant: INTEL CORPORATION
Inventor： Julien Sebot , William W. Macy, Jr. , Eric L. Debes , Huy V. Nguyen
CPC classification number: G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
Abstract translation: 用于使用SIMD合并指令执行比特流缓冲器操作的方法，装置和程序装置。 一个实施例的方法包括确定在第一数据块中是否存在用于部分可变长度符号的任何未处理的数据比特。 执行移位合并操作以将来自第一数据块的未处理数据位与第二数据块合并。 形成合并的数据块。 从合并的数据块中提取由未处理的数据位和来自第二数据块的多个数据位组成的合并的可变长度符号。
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公开(公告)号：US09858076B2
公开(公告)日：2018-01-02
申请号：US15393963
申请日：2016-12-29
Applicant: Intel Corporation
Inventor： William W. Macy, Jr. , Huy V. Nguyen
CPC classification number: G06F9/3016 , G06F9/3001 , G06F9/30014 , G06F9/30036 , G06F9/30101 , G06F9/30145 , G06F15/8007
Abstract: Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second block are corrected.
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公开(公告)号：US09678753B2
公开(公告)日：2017-06-13
申请号：US15066468
申请日：2016-03-10
Applicant: Intel Corporation
Inventor： William W. Macy, Jr. , Huy V. Nguyen
CPC classification number: G06F9/3016 , G06F9/3001 , G06F9/30014 , G06F9/30036 , G06F9/30101 , G06F9/30145 , G06F15/8007
Abstract: Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second block are corrected.
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