- 专利标题: PROCESSOR TO EXECUTE SHIFT RIGHT MERGE INSTRUCTIONS
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申请号: US16208534申请日: 2018-12-03
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公开(公告)号: US20190220280A1公开(公告)日: 2019-07-18
- 发明人: Julien Sebot , William W. Macy, JR. , Eric L. Debes , Huy V. Nguyen
- 申请人: Intel Corporation
- 主分类号: G06F9/30
- IPC分类号: G06F9/30 ; G06F15/80 ; G06F17/15 ; G06F17/14 ; G06F9/38
摘要:
Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
公开/授权文献
- US10732973B2 Processor to execute shift right merge instructions 公开/授权日:2020-08-04
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