公开(公告)号：US20240032441A1

公开(公告)日：2024-01-25

申请号：US17892162

申请日：2022-08-22

Applicant: United Microelectronics Corp.

Inventor： Chih-Wei Kuo ,  Hung-Chan Lin ,  Chung Yi Chiu

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/10 ,  H01L43/14

CPC classification number: H01L43/04 ,  H01L27/222 ,  H01L43/06 ,  H01L43/10 ,  H01L43/14

Abstract: Provided is a magnetoresistive random access memory (MRAM) device including a bottom electrode, a magnetic tunnel junction (MTJ) structure, a first spin orbit torque (SOT) layer, a cap layer, a second SOT layer, an etch stop layer, and an upper metal line layer. The MTJ structure is disposed on the bottom electrode. The first SOT layer is disposed on the MTJ structure. The cap layer is disposed on the first SOT layer. The second SOT layer is disposed on the cap layer. The etch stop layer is disposed on the second SOT layer. The upper metal line layer penetrates though the etch stop layer and is landed on the second SOT layer.

公开(公告)号：US20240016067A1

公开(公告)日：2024-01-11

申请号：US17885521

申请日：2022-08-10

Applicant: United Microelectronics Corp.

Inventor： Chih-Wei Kuo ,  Chung Yi Chiu ,  Yi-Wei Tseng ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/14

CPC classification number: H01L43/04 ,  H01L27/222 ,  H01L43/06 ,  H01L43/14

Abstract: A magnetic memory including a substrate, a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ) stack, a first protection layer, and a second protection layer is provided. The SOT layer is located over the substrate. The MTJ stack is located on the SOT layer. The first protection layer and the second protection layer are located on the sidewall of the MTJ stack. The first protection layer is located between the second protection layer and the MTJ stack. There is a notch between the second protection layer and the SOT layer.

公开(公告)号：US11818966B2

公开(公告)日：2023-11-14

申请号：US17541280

申请日：2021-12-03

Applicant: United Microelectronics Corp.

Inventor： Yi Yu Lin ,  Po Kai Hsu ,  Chun-Hao Wang ,  Yu-Ru Yang ,  Ju Chun Fan ,  Chung Yi Chiu

IPC: G11C13/00 ,  H10N70/00 ,  H10B63/00

CPC classification number: H10N70/043 ,  H10B63/30 ,  H10N70/061 ,  H10N70/841 ,  H10N70/861

Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a substrate having a pillar protruding from a surface of the substrate, a gate surrounding a part of a side surface of the pillar, a gate dielectric layer, a first electrode, a second electrode, a variable resistance layer, a first doped region and a second doped region. The gate dielectric layer is disposed between the gate and the pillar. The first electrode is disposed on a top surface of the pillar. The second electrode is disposed on the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The first doped region is disposed in the pillar below the gate and in a part of the substrate below the pillar. The second doped region is disposed in the pillar between the gate and the first electrode.

公开(公告)号：US11329161B2

公开(公告)日：2022-05-10

申请号：US16907001

申请日：2020-06-19

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L29/786 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8232 ,  H01L21/225 ,  H01L29/749

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

公开(公告)号：US20210351302A1

公开(公告)日：2021-11-11

申请号：US16907001

申请日：2020-06-19

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

公开(公告)号：US20220216345A1

公开(公告)日：2022-07-07

申请号：US17705380

申请日：2022-03-27

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8232 ,  H01L21/225 ,  H01L21/762 ,  H01L29/749

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

公开(公告)号：US11804550B2

公开(公告)日：2023-10-31

申请号：US17705376

申请日：2022-03-27

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L29/06 ,  H01L21/8232 ,  H01L21/225 ,  H01L21/762 ,  H01L29/749 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78603 ,  H01L21/2253 ,  H01L21/762 ,  H01L21/8232 ,  H01L29/0653 ,  H01L29/66772 ,  H01L29/749

Abstract: A method for fabricating a field-effect transistor includes the following steps. A gate structure layer in a line shape including a first region and a second region abutting to the first region is formed on a silicon layer. A first implanting process is performed to implant first-type dopants at least into a second portion of the second region of the gate structure layer. A second implanting region is performed to implant second-type dopants into the silicon layer to form a source region and a second region corresponding to the first region of the gate structure layer. The gate structure layer has a conductive-type junction at an interface between the first and second portions of the second region. A width of the silicon layer under the second region of the gate structure layer is smaller than a width of the gate structure layer.

公开(公告)号：US11799031B2

公开(公告)日：2023-10-24

申请号：US17705380

申请日：2022-03-27

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L21/8232 ,  H01L21/762 ,  H01L29/749 ,  H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L21/225

CPC classification number: H01L29/78603 ,  H01L21/2253 ,  H01L21/762 ,  H01L21/8232 ,  H01L29/0653 ,  H01L29/66772 ,  H01L29/749

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

公开(公告)号：US20230135098A1

公开(公告)日：2023-05-04

申请号：US17541280

申请日：2021-12-03

Applicant: United Microelectronics Corp.

Inventor： Yi Yu Lin ,  Po Kai Hsu ,  Chun-Hao Wang ,  Yu-Ru Yang ,  Ju Chun Fan ,  Chung Yi Chiu

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a substrate having a pillar protruding from a surface of the substrate, a gate surrounding a part of a side surface of the pillar, a gate dielectric layer, a first electrode, a second electrode, a variable resistance layer, a first doped region and a second doped region. The gate dielectric layer is disposed between the gate and the pillar. The first electrode is disposed on a top surface of the pillar. The second electrode is disposed on the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The first doped region is disposed in the pillar below the gate and in a part of the substrate below the pillar. The second doped region is disposed in the pillar between the gate and the first electrode.

公开(公告)号：US20220216344A1

公开(公告)日：2022-07-07

申请号：US17705376

申请日：2022-03-27

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8232 ,  H01L21/225 ,  H01L21/762 ,  H01L29/749

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.