公开(公告)号：US12010926B2

公开(公告)日：2024-06-11

申请号：US18138137

申请日：2023-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A method of manufacturing a magnetic tunnel junction (MTJ) device, including steps of forming a dielectric layer comprising a metal line therein on a substrate, forming a magnetic tunneling junction element over the metal line, depositing a silicon nitride cap layer conformally covering the magnetic tunneling junction element and the dielectric layer, depositing a tantalum containing cap layer conformally covering the silicon nitride cap layer, removing parts of the tantalum containing cap layer and the silicon nitride cap layer, and disposing a metal plug directly on the magnetic tunneling junction element.

公开(公告)号：US20230301201A1

公开(公告)日：2023-09-21

申请号：US18201741

申请日：2023-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu

IPC: H10N50/80 ,  H01L27/02 ,  H10B61/00

CPC classification number: H10N50/80 ,  H01L27/0248 ,  H10B61/22

Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

公开(公告)号：US11706995B2

公开(公告)日：2023-07-18

申请号：US17165837

申请日：2021-02-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu

IPC: H10N50/80 ,  H01L27/02 ,  H10B61/00

CPC classification number: H10N50/80 ,  H01L27/0248 ,  H10B61/22

Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

公开(公告)号：US11631805B2

公开(公告)日：2023-04-18

申请号：US17121658

申请日：2020-12-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method for forming a semiconductor device includes the steps of providing a substrate having a memory region and a logic region, forming a memory stack structure on the memory region, forming a passivation layer covering a top surface and sidewalls of the memory stack structure, forming a first interlayer dielectric layer on the passivation layer, performing a post-polishing etching back process to remove a portion of the first interlayer dielectric layer and a portion of the passivation layer on the top surface of the memory stack structure, forming a second interlayer dielectric layer on the first interlayer dielectric layer and directly contacting the passivation layer, and forming an upper contact structure through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure to contact the memory stack structure.

公开(公告)号：US11522129B2

公开(公告)日：2022-12-06

申请号：US17084639

申请日：2020-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo

IPC: H01L45/00 ,  H01L27/24

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a resistance random access memory (RRAM), a first spacer located at two sides of the RRAM, a second spacer located outside the first spacer, wherein the second spacer contains metal material or metal oxide material, and a third spacer located outside the second spacer.

公开(公告)号：US20220216395A1

公开(公告)日：2022-07-07

申请号：US17165837

申请日：2021-02-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu

IPC: H01L43/02 ,  H01L27/22

Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

公开(公告)号：US10903269B2

公开(公告)日：2021-01-26

申请号：US16504345

申请日：2019-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L27/22 ,  H01L43/02 ,  H01L21/768 ,  H01L43/12

Abstract: A magnetic memory device includes a first dielectric layer on a substrate, first and second via plugs in the first dielectric layer, first and second cylindrical memory stacks on the first and second via plugs, respectively, and an insulating cap layer conformally disposed on the first dielectric layer and on sidewalls of the first and second cylindrical memory stacks. The insulating cap layer is not disposed in a logic area and a via forming region between the first and second cylindrical memory stacks.

公开(公告)号：US20210013395A1

公开(公告)日：2021-01-14

申请号：US16529740

申请日：2019-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Ting-Hsiang Huang ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L43/02

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a metal interconnection. The two magnetic tunnel junction elements are arranged side by side at a first direction. The metal interconnection is disposed between the magnetic tunnel junction elements, wherein the metal interconnection includes a contact plug part having a long shape at a top view, and the long shape has a length at a second direction larger than a width at the first direction, wherein the second direction is orthogonal to the first direction.

公开(公告)号：US09779942B1

公开(公告)日：2017-10-03

申请号：US15220386

申请日：2016-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L21/033 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/31144

Abstract: A method of forming a patterned mask layer includes the following steps. A plurality of support features is formed on a mask layer. A plurality of spacers is formed on side walls of the support features. A patterned protection layer is formed on the support features and top surfaces of the spacers. At least a part of side surfaces of the spacers are not covered by the patterned protection layer, and the patterned protection layer is formed in a process environment containing methane (CH4). A trimming process is then performed to remove a part of each of the spacers. Tapered parts of the spacers may be removed by the trimming process before the step of etching the mask layer with the spacers as a mask, and the critical dimension uniformity of the patterned mask layer may be improved accordingly.

公开(公告)号：US20240016067A1

公开(公告)日：2024-01-11

申请号：US17885521

申请日：2022-08-10

Applicant: United Microelectronics Corp.

Inventor： Chih-Wei Kuo ,  Chung Yi Chiu ,  Yi-Wei Tseng ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/14

CPC classification number: H01L43/04 ,  H01L27/222 ,  H01L43/06 ,  H01L43/14

Abstract: A magnetic memory including a substrate, a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ) stack, a first protection layer, and a second protection layer is provided. The SOT layer is located over the substrate. The MTJ stack is located on the SOT layer. The first protection layer and the second protection layer are located on the sidewall of the MTJ stack. The first protection layer is located between the second protection layer and the MTJ stack. There is a notch between the second protection layer and the SOT layer.