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    Semiconductor Device With Multi Level Interconnects And Method Of Forming The Same
    4.
    发明申请
    Semiconductor Device With Multi Level Interconnects And Method Of Forming The Same 审中-公开
    具有多级互连的半导体器件及其形成方法

    公开(公告)号：US20140209984A1

    公开(公告)日：2014-07-31

    申请号：US13756389

    申请日：2013-01-31

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jeng Min Liang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Chi-Wen Liu ,  Kuo-Hsiu Wei ,  Kuo-Feng Huang

    IPC分类号： H01L23/485 ,  H01L21/768

    CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76855 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a gate structure separating source and drain (S/D) features. The semiconductor device further includes a first dielectric layer formed over the substrate, the first dielectric layer including a first interconnect structure in electrical contact with the S/D features. The semiconductor device further includes an intermediate layer formed over the first dielectric layer, the intermediate layer having a top surface that is substantially coplanar with a top surface of the first interconnect structure. The semiconductor device further includes a second dielectric layer formed over the intermediate layer, the second dielectric layer including a second interconnect structure in electrical contact with the first interconnect structure and a third interconnect structure in electrical contact with the gate structure.

    摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性半导体器件包括具有分离源极和漏极（S / D）特征的栅极结构的衬底。 半导体器件还包括形成在衬底上的第一介电层，第一介电层包括与S / D特征电接触的第一互连结构。 半导体器件还包括形成在第一介电层上的中间层，中间层具有与第一互连结构的顶表面基本上共面的顶表面。 半导体器件还包括形成在中间层上的第二介电层，第二介电层包括与第一互连结构电接触的第二互连结构和与栅极结构电接触的第三互连结构。