公开(公告)号：US20210391186A1

公开(公告)日：2021-12-16

申请号：US16902180

申请日：2020-06-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD

发明人： Ji Cui ,  Fu-Ming Huang ,  Ting-Kui Chang ,  Tang-Kuei Chang ,  Chun-Chieh Lin ,  Wei-Wei Liang ,  Liang-Guang Chen ,  Kei-Wei Chen ,  Hung Yen ,  Ting-Hsun Chang ,  Chi-Hsiang Shen ,  Li-Chieh Wu ,  Chi-Jen Liu

IPC分类号： H01L21/321 ,  B24B37/04 ,  B24B37/10 ,  C09G1/02

摘要： A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.

公开(公告)号：US20200051855A1

公开(公告)日：2020-02-13

申请号：US16655509

申请日：2019-10-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Hao Chung ,  Chang-Sheng Lin ,  Kuo-Feng Huang ,  Li-Chieh Wu ,  Chun-Chieh Lin

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L21/02

摘要： A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

公开(公告)号：US10163644B2

公开(公告)日：2018-12-25

申请号：US14175685

申请日：2014-02-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Rueijer Lin ,  Ya-Lien Lee ,  Chun-Chieh Lin ,  Hung-Wen Su

IPC分类号： H01L23/532 ,  H01L21/285 ,  H01L21/768

摘要： An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.

公开(公告)号：US10109523B2

公开(公告)日：2018-10-23

申请号：US15395057

申请日：2016-12-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Hao Chung ,  Chang-Sheng Lin ,  Kuo-Feng Huang ,  Li-Chieh Wu ,  Chun-Chieh Lin

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/535

摘要： A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

公开(公告)号：US20170304990A1

公开(公告)日：2017-10-26

申请号：US15136706

申请日：2016-04-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ting-Kui Chang ,  Fu-Ming Huang ,  Liang-Guang Chen ,  Chun-Chieh Lin

IPC分类号： B24B37/20 ,  B24B37/005

CPC分类号： B24B37/20 ,  B24B37/005 ,  B24B37/30

摘要： A polisher head of a polishing apparatus includes a membrane and a first local pressure nodule and a second local pressure nodule physically contacting the membrane. The first local pressure nodule is configured to apply a first local force to the membrane and the second local pressure nodule is configured to apply a second local force to the membrane. The first local pressure nodule and the second local pressure nodule are independently controllable.

公开(公告)号：US09659856B2

公开(公告)日：2017-05-23

申请号：US14523256

申请日：2014-10-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ya-Lien Lee ,  Chun-Chieh Lin

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/76813 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76879 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a first conductive line, a dielectric layer over the first conductive line, a diffusion barrier layer in the dielectric layer, and a second conductive line in the dielectric layer. The second conductive line includes a first portion of the diffusion barrier layer. A via is underlying the second conductive line and electrically couples the second conductive line to the first conductive line. The via includes a second portion of the diffusion barrier layer, with the second portion of the diffusion barrier layer having a bottom end higher than a bottom surface of the via.

公开(公告)号：US09520362B2

公开(公告)日：2016-12-13

申请号：US14706311

申请日：2015-05-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L29/51 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/511 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括形成具有多个第一开口的图案化电介质层。 该方法包括在图案化的介电层上形成导电衬垫层，导电衬垫层部分填充第一开口。 该方法包括在第一开口之外的导电衬垫层的部分上形成沟槽掩模层，从而形成多个第二开口，其中一部分形成在第一开口上。 该方法包括在第一开口中沉积导电材料以形成多个通孔，并且在第二开口中形成多个金属线。 该方法包括去除沟槽掩模层。

公开(公告)号：US20160133514A1

公开(公告)日：2016-05-12

申请号：US14988005

申请日：2016-01-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chien-An Chen ,  Wen-Jiun Liu ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76864 ,  H01L21/76882 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a conductive structure includes forming a first opening and a second opening in a dielectric layer on a substrate, wherein the first opening is narrower than the second opening. The method further includes depositing a diffusion barrier layer to line the first opening and the second opening. The method further includes forming a metal layer over the diffusion barrier layer to fill at least portions of the first opening and the second opening, wherein a maximum thickness of the metal layer in the first opening is greater than a maximum thickness of the metal layer in the second opening.

摘要翻译： 形成导电结构的方法包括在基板上的电介质层中形成第一开口和第二开口，其中第一开口比第二开口窄。 该方法还包括沉积扩散阻挡层以使第一开口和第二开口线对齐。 该方法还包括在扩散阻挡层上形成金属层以填充第一开口和第二开口的至少部分，其中第一开口中的金属层的最大厚度大于金属层的最大厚度 第二个开幕。

公开(公告)号：US20140273470A1

公开(公告)日：2014-09-18

申请号：US13925495

申请日：2013-06-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Rueijer Lin ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai

IPC分类号： H01L21/308

CPC分类号： B81C1/00158 ,  B81B7/008 ,  B81B2207/015 ,  B81B2207/096 ,  B81C1/00246 ,  B81C1/00333 ,  B81C1/00539 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2203/0118 ,  B81C2203/0127 ,  B81C2203/0742 ,  B81C2203/0778 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02247 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802

摘要： Disclosed is a method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N2/H2 plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.

摘要翻译： 公开了在制造半导体器件期间形成互连的镶嵌工艺中形成氮化钛（TiN）硬掩模的方法，同时控制由TiN硬掩模承载的应力的类型和大小。 TiN硬掩模以多层结构形成，其中通过重复包括TiN和氯PECVD沉积以及N2 / H2等离子体气体处理的工艺循环来连续形成每个子层。 在其形成期间，通过控制TiN子层的数量和等离子体气体处理持续时间来控制由TiN硬掩模承载的应力，使得应力可以平衡在常规制备的TiN硬掩模上预期的预定外部应力 ，这导致沟槽侧壁变形，沟槽开口收缩和间隙填充问题。

公开(公告)号：US11658065B2

公开(公告)日：2023-05-23

申请号：US16902203

申请日：2020-06-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Ji Cui ,  Fu-Ming Huang ,  Ting-Kui Chang ,  Tang-Kuei Chang ,  Chun-Chieh Lin ,  Wei-Wei Liang ,  Chi-Hsiang Shen ,  Ting-Hsun Chang ,  Li-Chieh Wu ,  Hung Yen ,  Chi-Jen Liu ,  Liang-Guang Chen ,  Kei-Wei Chen

IPC分类号： H01L21/768 ,  C09K3/14 ,  C09G1/02 ,  H01L21/321

CPC分类号： H01L21/7684 ,  C09G1/02 ,  C09K3/1463 ,  C09K3/1481 ,  H01L21/3212 ,  H01L21/76877

摘要： A method for CMP includes following operations. A metal layer is received. A CMP slurry composition is provided in a CMP apparatus. The CMP slurry composition includes at least a first oxidizer and a second oxidizer different from each other. The first oxidizer is oxidized to form a peroxidant by the second oxidizer. A portion of the metal layer is oxidized to form a first metal oxide by the peroxidant. The first metal oxide is re-oxidized to form a second metal oxide by the second oxidizer.