公开(公告)号：US12211843B2

公开(公告)日：2025-01-28

申请号：US17701712

申请日：2022-03-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hsiung Tsai ,  Ziwei Fang ,  Tsan-Chun Wang ,  Kei-Wei Chen

IPC: H01L29/06 ,  H01L21/306 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. The at least one gate stack is disposed over the insulators and over the channel portions of the fins. The epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. The epitaxy material portions disposed on the flank portions of the fins are separate from one another.

公开(公告)号：US12046661B2

公开(公告)日：2024-07-23

申请号：US17200905

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Kei-Wei Chen

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type field effect transistor including a substrate, insulators, a gate stack, a first spacer, a second spacer, and a third spacer is described. The substrate has fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and over the insulators. The first spacer is located over the sidewall of the gate stack. The second spacer is located over the first spacer. The first spacer and the second spacer includes carbon. The third spacer is located between the first spacer and the second spacer.

公开(公告)号：US20240050995A1

公开(公告)日：2024-02-15

申请号：US17887718

申请日：2022-08-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Wen Liu ,  Yeo-Sin Lin ,  Shu-Wei Hsu ,  Che-Hao Tu ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: B08B3/10 ,  B08B1/00 ,  B24B37/04 ,  B24B37/10 ,  B24B37/30 ,  B24B57/02

CPC classification number: B08B3/10 ,  B08B1/002 ,  B24B37/044 ,  B24B37/046 ,  B24B37/105 ,  B24B37/30 ,  B24B57/02

Abstract: A process tool including a polishing pad on a top surface of a wafer platen. A wafer carrier is configured to hold a wafer over the polishing pad. A slurry dispenser is configured to dispense an abrasive slurry including a plurality of charged abrasive particles having a first polarity onto the polishing pad. A first conductive rod is within the wafer platen and coupled to a first voltage supply. A wafer roller is configured to support the wafer. A first wafer brush is arranged beside the wafer roller. A second conductive rod is within the first wafer brush and coupled to a second voltage supply. The first voltage supply is configured to apply a first charge having a second polarity, opposite the first polarity, to the first conductive rod. The second voltage supply is configured to apply a second charge having the second polarity to the second conductive rod.

公开(公告)号：US11450742B2

公开(公告)日：2022-09-20

申请号：US15796060

申请日：2017-10-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hsiung Tsai ,  Lai-Wan Chong ,  Chien-Wei Lee ,  Kei-Wei Chen

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265

Abstract: Present disclosure provides a FinFET structure, including a fin and a gate surrounding a first portion of the fin. A dopant concentration in the first portion of the fin is lower than about 1E17/cm3. The FinFET structure further includes an insulating layer surrounding a second portion of the fin. The dopant concentration of the second portion of the fin is greater than about 8E15/cm3. The insulating layer includes a lower layer and an upper layer, and the lower layer is disposed over a substrate connecting to the fin and has a dopant concentration greater than about 1E19/cm3.

公开(公告)号：US11417566B2

公开(公告)日：2022-08-16

申请号：US16382641

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hao Kung ,  Chih-Chieh Chang ,  Kao-Feng Liao ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/02

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

公开(公告)号：US20210202718A1

公开(公告)日：2021-07-01

申请号：US17200905

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Kei-Wei Chen

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

Abstract: A fin-type field effect transistor including a substrate, insulators, a gate stack, a first spacer, a second spacer, and a third spacer is described. The substrate has fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and over the insulators. The first spacer is located over the sidewall of the gate stack. The second spacer is located over the first spacer. The first spacer and the second spacer includes carbon. The third spacer is located between the first spacer and the second spacer.

公开(公告)号：US20210202239A1

公开(公告)日：2021-07-01

申请号：US16727533

申请日：2019-12-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hui-Chi Huang ,  Jeng-Chi Lin ,  Pin-Chuan Su ,  Chien-Ming Wang ,  Kei-Wei Chen

IPC: H01L21/02 ,  B08B7/04 ,  B08B1/00 ,  B08B1/04 ,  B08B3/08 ,  B08B5/04 ,  A46B13/04

Abstract: A tool and methods of removing films from bevel regions of wafers are disclosed. The bevel film removal tool includes an inner motor nested within an outer motor and a bevel brush secured to the outer motor. The bevel brush is adjustable radially outward to allow the wafer to be inserted in the bevel brush and to be secured to the inner motor. The bevel brush is adjustable radially inward to engage one or more sections of the bevel brush and to bring the bevel brush in contact with a bevel region of the wafer. Once engaged, a solution may be dispensed at the engaged sections of the bevel brush and the inner motor and the outer motor may be rotated such that the bevel brush is rotated against the wafer such that the bevel films of the wafer are both chemically and mechanically removed.

公开(公告)号：US10953514B1

公开(公告)日：2021-03-23

申请号：US16572895

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shang-Yu Wang ,  Chun-Hao Kung ,  Ching-Hsiang Tsai ,  Kei-Wei Chen ,  Hui-Chi Huang

IPC: B24B37/005 ,  H01L21/304 ,  B24B37/10 ,  H01L21/306 ,  B24B37/04

Abstract: A method includes placing a polisher head on platen, the polisher head including a set of first magnets, and controlling a set of second magnets to rotate the polisher head on the platen, wherein controlling the set of second magnets includes reversing the polarity of at least one second magnet of the set of second magnets to produce a magnetic force on at least one first magnet of the set of first magnets, wherein the set of second magnets are external to the polisher head.

公开(公告)号：US20210053180A1

公开(公告)日：2021-02-25

申请号：US16550021

申请日：2019-08-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Michael Yen ,  Kao-Feng Liao ,  Hsin-Ying Ho ,  Chun-Wen Hsiao ,  Sheng-Chao Chuang ,  Ting-Hsun Chang ,  Fu-Ming Huang ,  Chun-Chieh Lin ,  Peng-Chung Jangjian ,  Ji James Cui ,  Liang-Guang Chen ,  Chih Hung Chen ,  Kei-Wei Chen

IPC: B24B37/26 ,  B24B37/24 ,  B24B37/005

Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.

公开(公告)号：US20210020449A1

公开(公告)日：2021-01-21

申请号：US16515938

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Te-Chien Hou ,  Yu-Ting Yen ,  Cheng-Yu Kuo ,  Chih Hung Chen ,  William Weilun Hong ,  Kei-Wei Chen

IPC: H01L21/3105 ,  H01L29/66 ,  B24B37/04 ,  B24B37/20

Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.