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公开(公告)号：US12174415B2
公开(公告)日：2024-12-24
申请号：US17883642
申请日：2022-08-09
Inventor： Chih-Chieh Chang , Chung-Hao Tsai , Chen-Hua Yu , Chuei-Tang Wang
Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. The encapsulant laterally encapsulates the photonic die. The wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.
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公开(公告)号：US11043396B2
公开(公告)日：2021-06-22
申请号：US16179307
申请日：2018-11-02
Inventor： Chun-Hao Kung , Tung-Kai Chen , Chih-Chieh Chang , Kao-Feng Liao , Hui-Chi Huang , Kei-Wei Chen
IPC: H01L21/321 , H01L21/768 , C09G1/02 , C09G1/04 , H01L21/306
Abstract: Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.
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公开(公告)号：US12131944B2
公开(公告)日：2024-10-29
申请号：US17460929
申请日：2021-08-30
Inventor： Chun-Wei Hsu , Chih-Chieh Chang , Yi-Sheng Lin , Jian-Ci Lin , Jeng-Chi Lin , Ting-Hsun Chang , Liang-Guang Chen , Ji Cui , Kei-Wei Chen , Chi-Jen Liu
IPC: H01L21/768 , C09G1/02 , H01L23/522
CPC classification number: H01L21/7684 , C09G1/02 , H01L21/76877 , H01L23/5226
Abstract: A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.
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公开(公告)号：US20240061195A1
公开(公告)日：2024-02-22
申请号：US18497999
申请日：2023-10-30
Inventor： Chih-Chieh Chang , Chung-Hao Tsai , Chen-Hua Yu , Chuei-Tang Wang
CPC classification number: G02B6/4274 , H01L25/167 , H01L24/20 , H01L23/3128 , H01L23/5383 , H01L23/5386 , H01L24/19 , H01L21/4853 , H01L21/4857 , H01L21/565 , G02B6/4239 , G02B6/4202 , H01L23/5389 , H01L2224/214
Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a first package component and an optical signal port disposed aside the first package component. The first package component includes a first die including an electronic integrated circuit, a first insulating encapsulation laterally covering the first die, a redistribution structure disposed on the first die and the first insulating encapsulation, and a second die including a photonic integrated circuit and electrically coupled to the first die through the redistribution structure. The optical signal port is optically coupled to an edge facet of the second die of the first package component.
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公开(公告)号：US11460633B2
公开(公告)日：2022-10-04
申请号：US17214920
申请日：2021-03-28
Inventor： Chih-Chieh Chang , Chung-Hao Tsai , Chen-Hua Yu , Chuei-Tang Wang
Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. The encapsulant laterally encapsulates the photonic die. The wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.
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Patent Agency Ranking
公开(公告)号：US10267990B1
公开(公告)日：2019-04-23
申请号：US16205432
申请日：2018-11-30
Inventor： Chen-Hua Yu , Chuei-Tang Wang , Hsing-Kuo Hsia , Yu-Kuang Liao , Chih-Chieh Chang
Abstract: In an embodiment, a method includes: forming an interconnect including waveguides and conductive features disposed in a plurality of dielectric layers, the conductive features including conductive lines and vias, the waveguides formed of a first material having a first refractive index, the dielectric layers formed of a second material having a second refractive index less than the first refractive index; bonding a plurality of dies to a first side of the interconnect, the dies electrically connected by the conductive features, the dies optically connected by the waveguides; and forming a plurality of conductive connectors on a second side of the interconnect, the conductive connectors electrically connected to the dies by the conductive features.
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公开(公告)号：US12100698B2
公开(公告)日：2024-09-24
申请号：US17407142
申请日：2021-08-19
Inventor： Chih-Chieh Chang , Chung-Hao Tsai , Chen-Hua Yu , Chuei-Tang Wang
CPC classification number: H01L25/167 , H01L23/481 , H01L24/08 , H01L24/73 , H01L33/58 , H01L33/62 , H01L2224/08145 , H01L2224/73204
Abstract: Semiconductor device includes light-emitting die and semiconductor package. Light emitting die includes substrate and first conductive pad. Substrate has emission region located at side surface. First conductive pad is located at bottom surface of substrate. Semiconductor package includes semiconductor-on-insulator substrate, interconnection structure, second conductive pad, and through semiconductor via. Semiconductor-on-insulator substrate has linear waveguide formed therein. Interconnection structure is disposed on semiconductor-on-insulator substrate. Edge coupler is embedded within interconnection structure and is connected to linear waveguide. Semiconductor-on-insulator substrate and interconnection structure include recess in which light-emitting die is disposed. Edge coupler is located close to sidewall of recess. Second conductive pad is located at bottom of recess. Through semiconductor via extends across semiconductor-on-insulator substrate to contact second conductive pad. First conductive pad is connected to through semiconductor via. Emission region directly faces sidewall of recess where edge coupler is located.
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公开(公告)号：US11830841B2
公开(公告)日：2023-11-28
申请号：US17729728
申请日：2022-04-26
Inventor： Chuei-Tang Wang , Chih-Chieh Chang , Yu-Kuang Liao , Hsing-Kuo Hsia , Chih-Yuan Chang , Jeng-Shien Hsieh , Chen-Hua Yu
IPC: H01L23/00 , H01L21/304 , H01L21/306 , H01L21/44 , H01L23/31 , H01L23/522 , H01L23/498 , H01L25/00 , H01L21/683
CPC classification number: H01L24/17 , H01L21/304 , H01L21/30604 , H01L21/44 , H01L21/6835 , H01L23/3107 , H01L23/3128 , H01L23/49811 , H01L23/5226 , H01L24/03 , H01L24/09 , H01L24/11 , H01L25/00 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L2221/6834 , H01L2221/68327 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/92125 , H01L2225/06517 , H01L2225/06534 , H01L2225/06572 , H01L2924/15311
Abstract: A semiconductor package includes an interconnect structure, an insulating layer and a conductive layer. The interconnect structure includes a first surface and a second surface opposite to the first surface. The insulating layer contacts the interconnect structure. The insulating layer includes a third surface contacting the second surface of the interconnect structure and a fourth surface opposite to the third surface. The conductive layer is electrically coupled to the interconnect structure. The conductive layer has a continuous portion extending from the second surface to the fourth surface.
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公开(公告)号：US11373879B2
公开(公告)日：2022-06-28
申请号：US17019234
申请日：2020-09-12
Inventor： Tung-Kai Chen , Ching-Hsiang Tsai , Kao-Feng Liao , Chih-Chieh Chang , Chun-Hao Kung , Fang-I Chih , Hsin-Ying Ho , Chia-Jung Hsu , Hui-Chi Huang , Kei-Wei Chen
IPC: H01L21/321 , H01L21/3105 , H01L21/28
Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
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公开(公告)号：US11322470B2
公开(公告)日：2022-05-03
申请号：US16879556
申请日：2020-05-20
Inventor： Chuei-Tang Wang , Chih-Chieh Chang , Yu-Kuang Liao , Hsing-Kuo Hsia , Chih-Yuan Chang , Jeng-Shien Hsieh , Chen-Hua Yu
IPC: H01L23/00 , H01L21/304 , H01L21/306 , H01L21/44 , H01L23/31 , H01L23/522 , H01L23/498 , H01L25/00 , H01L21/683
Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, an insulating layer contacting the second surface of the interconnect structure wherein the insulating layer has a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface, at least one optical chip over the fourth surface of the insulating layer and electrically coupled to the interconnect structure, and a molding compound over the first surface of the interconnect structure.
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