公开(公告)号：US20250067926A1

公开(公告)日：2025-02-27

申请号：US18948506

申请日：2024-11-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chieh Chang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/13

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. The encapsulant laterally encapsulates the photonic die. The wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.

公开(公告)号：US12176282B2

公开(公告)日：2024-12-24

申请号：US18190935

申请日：2023-03-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Ming Weng ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Hung-Yi Kuo ,  Tsung-Yuan Yu ,  Hua-Kuei Lin ,  Hsiu-Jen Lin ,  Ming-Che Ho ,  Yu-Hsiang Hu ,  Chewn-Pu Jou ,  Cheng-Tse Tang

IPC: H01L23/498 ,  G02B6/42 ,  H01L21/768 ,  H01L23/00

Abstract: A manufacturing method of a semiconductor package includes the following steps. A supporting layer is formed over a redistribution structure. A first planarization process is performed over the supporting layer. A lower dielectric layer is formed over the supporting layer, wherein the lower dielectric layer includes a concave exposing a device mounting region of the supporting layer. A first sacrificial layer is formed over the supporting layer, wherein the sacrificial layer filling the concave. A second planarization process is performed over the lower dielectric layer and the first sacrificial layer. A transition waveguide provided over the lower dielectric layer. The first sacrificial layer is removed. A semiconductor device is mounted over the device mounting region, wherein the semiconductor device includes a device waveguide is optically coupled to the transition waveguide.

公开(公告)号：US12174415B2

公开(公告)日：2024-12-24

申请号：US17883642

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chieh Chang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang

IPC: G02B6/12 ,  G02B6/13

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. The encapsulant laterally encapsulates the photonic die. The wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.

公开(公告)号：US20240387417A1

公开(公告)日：2024-11-21

申请号：US18789693

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01Q1/22 ,  H01Q21/00

Abstract: A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The first die, the second die and the third die are molded in a molding compound. The first redistribution layer is disposed on the molding compound and is electrically connected to the first die, the second die and the third die. The antenna is located on the molding compound and electrically connected to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna. The conductive elements are connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound.

公开(公告)号：US12125812B2

公开(公告)日：2024-10-22

申请号：US17676866

申请日：2022-02-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Yuan Huang ,  Shih-Chang Ku ,  Chuei-Tang Wang ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/36 ,  H01L23/52 ,  H01L23/522 ,  H01L29/40

CPC classification number: H01L24/08 ,  H01L23/36 ,  H01L23/5226 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: An integrated circuit package includes first and second dies bonded to each other. The first die includes first die pads over a first device, first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads and electrically insulated from the second one of the first die pads or the second one of the first bonding pads. The second die includes second bonding pads. The first one of the first bonding pads is connected to a first one of the second bonding pads. The second one of the first bonding pads is connected to a second one of the second bonding pads.

公开(公告)号：US12057406B2

公开(公告)日：2024-08-06

申请号：US17832701

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chun-Hui Yu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/365

Abstract: Provided is a package including: a die having an upper surface and including at least one conductive pad disposed adjacent to the upper surface; a first pillar structure over the die; and a second pillar structure aside the first pillar structure, wherein the second pillar structure is electrically connected to the conductive pad of the die, and defining a recess portion recessed from a side surface of the second pillar structure, wherein the second pillar structure and the conductive pad have different conductivities.

公开(公告)号：US12057359B2

公开(公告)日：2024-08-06

申请号：US17884499

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Cheng Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  B29C45/14 ,  B29K63/00 ,  B29L31/34

CPC classification number: H01L23/3114 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/566 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0655 ,  B29C45/14655 ,  B29K2063/00 ,  B29K2995/0007 ,  B29L2031/3406 ,  H01L24/13 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81192 ,  H01L2924/1431 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19101 ,  H01L2924/3511 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/13113 ,  H01L2924/00014 ,  H01L2224/13118 ,  H01L2924/00014 ,  H01L2224/13149 ,  H01L2924/00014 ,  H01L2224/1312 ,  H01L2924/00014 ,  H01L2224/13109 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/1431 ,  H01L2924/00012

Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

公开(公告)号：US20240250002A1

公开(公告)日：2024-07-25

申请号：US18623992

申请日：2024-04-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L23/3121 ,  H01L24/09 ,  H01L24/17 ,  H01L24/33 ,  H01L2224/02372

Abstract: A semiconductor device includes a first die including a patterned conductive pad, a second die stacked over and electrically coupled to the first die, a bonding dielectric layer between the first and second dies, and a through die via penetrating through the first die and passing through the patterned conductive pad and the bonding dielectric layer. The second die includes a conductive pad directly over the patterned conductive pad. The bonding dielectric layer bonds the patterned conductive pad to the conductive pad, and the through die via directly lands on the conductive pad.

公开(公告)号：US20240222307A1

公开(公告)日：2024-07-04

申请号：US18603779

申请日：2024-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hsun Chen ,  Shou-Yi Wang ,  Jiun Yi Wu ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H01L25/18

CPC classification number: H01L24/24 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/19 ,  H01L24/81 ,  H01L25/18 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/6627 ,  H01L2224/24137 ,  H01L2224/24225 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: In an embodiment, a device includes: a semiconductor device; and a redistribution structure including: a first dielectric layer; a first grounding feature on the first dielectric layer; a second grounding feature on the first dielectric layer; a first pair of transmission lines on the first dielectric layer, the first pair of transmission lines being laterally disposed between the first grounding feature and the second grounding feature, the first pair of transmission lines being electrically coupled to the semiconductor device; a second dielectric layer on the first grounding feature, the second grounding feature, and the first pair of transmission lines; and a third grounding feature extending laterally along and through the second dielectric layer, the third grounding feature being physically and electrically coupled to the first grounding feature and the second grounding feature, where the first pair of transmission lines extend continuously along a length of the third grounding feature.

公开(公告)号：US12027446B2

公开(公告)日：2024-07-02

申请号：US17984254

申请日：2022-11-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Liang Shao ,  Lawrence Chiang Sheu ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Yi-Li Hsiao

IPC: H01L23/473 ,  H01L23/467

CPC classification number: H01L23/473 ,  H01L23/467

Abstract: An apparatus includes a semiconductor component and a cooling structure. The cooling structure is over a back side of the semiconductor component. The cooling structure includes a housing, a liquid delivery device and a gas exhaust device. The housing includes a cooling space adjacent to the semiconductor component. The liquid delivery device is connected to an inlet of the housing and is configured to deliver a liquid coolant into the cooling space from the inlet. The gas exhaust device is connected to an outlet of the housing and is configured to lower a pressure in the housing.