公开(公告)号：US20240162159A1

公开(公告)日：2024-05-16

申请号：US18423166

申请日：2024-01-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang WANG ,  Wei-Ting Chen ,  Chien-Hsun Chen ,  Shih-Ya Huang

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/95001

Abstract: Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.

公开(公告)号：US11923315B2

公开(公告)日：2024-03-05

申请号：US17372565

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Wei-Ting Chen ,  Chien-Hsun Chen ,  Shih-Ya Huang

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/95001

Abstract: Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.

公开(公告)号：US11217497B2

公开(公告)日：2022-01-04

申请号：US16882995

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Ling Tsai ,  Jiun Yi Wu ,  Chien-Hsun Lee ,  Chung-Shi Liu

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/498

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

公开(公告)号：US10971446B2

公开(公告)日：2021-04-06

申请号：US16458374

申请日：2019-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chien-Hsun Chen

IPC: H01L23/522 ,  H01L25/16 ,  H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768

Abstract: A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.

公开(公告)号：US20240222307A1

公开(公告)日：2024-07-04

申请号：US18603779

申请日：2024-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hsun Chen ,  Shou-Yi Wang ,  Jiun Yi Wu ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H01L25/18

CPC classification number: H01L24/24 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/19 ,  H01L24/81 ,  H01L25/18 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/6627 ,  H01L2224/24137 ,  H01L2224/24225 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: In an embodiment, a device includes: a semiconductor device; and a redistribution structure including: a first dielectric layer; a first grounding feature on the first dielectric layer; a second grounding feature on the first dielectric layer; a first pair of transmission lines on the first dielectric layer, the first pair of transmission lines being laterally disposed between the first grounding feature and the second grounding feature, the first pair of transmission lines being electrically coupled to the semiconductor device; a second dielectric layer on the first grounding feature, the second grounding feature, and the first pair of transmission lines; and a third grounding feature extending laterally along and through the second dielectric layer, the third grounding feature being physically and electrically coupled to the first grounding feature and the second grounding feature, where the first pair of transmission lines extend continuously along a length of the third grounding feature.

公开(公告)号：US11239193B2

公开(公告)日：2022-02-01

申请号：US16745933

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hsun Chen ,  Shou-Yi Wang ,  Jiun Yi Wu ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L23/66 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L25/18

Abstract: In an embodiment, a device includes: a semiconductor device; and a redistribution structure including: a first dielectric layer; a first grounding feature on the first dielectric layer; a second grounding feature on the first dielectric layer; a first pair of transmission lines on the first dielectric layer, the first pair of transmission lines being laterally disposed between the first grounding feature and the second grounding feature, the first pair of transmission lines being electrically coupled to the semiconductor device; a second dielectric layer on the first grounding feature, the second grounding feature, and the first pair of transmission lines; and a third grounding feature extending laterally along and through the second dielectric layer, the third grounding feature being physically and electrically coupled to the first grounding feature and the second grounding feature, where the first pair of transmission lines extend continuously along a length of the third grounding feature.

公开(公告)号：US11195788B2

公开(公告)日：2021-12-07

申请号：US16656642

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hsun Chen ,  Jiun Yi Wu ,  Chen-Hua Yu

IPC: H05K3/40 ,  H01L23/498 ,  H01L21/48 ,  H01L23/66

Abstract: A method includes forming a first redistribution line, forming a polymer layer including a first portion encircling the first redistribution line and a second portion overlapping the first redistribution line, forming a pair of differential transmission lines over and contacting the polymer layer, and molding the pair of differential transmission lines in a molding compound. The molding compound includes a first portion encircling the pair of differential transmission lines, and a second portion overlapping the pair of differential transmission lines. An electrical connector is formed over and electrically coupling to the pair of differential transmission lines.

公开(公告)号：US20210118787A1

公开(公告)日：2021-04-22

申请号：US16656642

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hsun Chen ,  Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/66

Abstract: A method includes forming a first redistribution line, forming a polymer layer including a first portion encircling the first redistribution line and a second portion overlapping the first redistribution line, forming a pair of differential transmission lines over and contacting the polymer layer, and molding the pair of differential transmission lines in a molding compound. The molding compound includes a first portion encircling the pair of differential transmission lines, and a second portion overlapping the pair of differential transmission lines. An electrical connector is formed over and electrically coupling to the pair of differential transmission lines.

公开(公告)号：US20200176378A1

公开(公告)日：2020-06-04

申请号：US16458374

申请日：2019-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chien-Hsun Chen

IPC: H01L23/522 ,  H01L25/16 ,  H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768

Abstract: A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.

公开(公告)号：US11670575B2

公开(公告)日：2023-06-06

申请号：US17395450

申请日：2021-08-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hsun Chen ,  Jiun-Yi Wu ,  Shou-Yi Wang

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/14 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/92125

Abstract: A package structure, and a RDL structure are provided. The package structure incudes a die and a RDL structure electrically connected to the die. The RDL structure includes a first redistribution layer, a second redistribution layer and a third redistribution layer. The first redistribution layer includes a first ground plate. The second redistribution layer includes a second ground plate and a signal trace. The signal trace is laterally spaced from the second ground plate. The third redistribution layer includes a third ground plate. The third redistribution layer and the first redistribution layer are disposed on opposite sides of the second redistribution layer. The signal trace is staggered with at least one of the first ground plate and the third ground plate in a direction perpendicular to a top surface of the signal trace.