公开(公告)号：US11855211B2

公开(公告)日：2023-12-26

申请号：US17728492

申请日：2022-04-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shahaji B. More ,  Chun Hsiung Tsai

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L21/02521 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: In a method of manufacturing a semiconductor device, an upper fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a lower fin structure, a sacrificial gate structure is formed over the upper fin structure, a source/drain region of the upper fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, an inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers, and a source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. In etching the source/drain region, a part of the lower fin structure is also etched to form a recess, in which a (111) surface is exposed.

公开(公告)号：US20230343634A1

公开(公告)日：2023-10-26

申请号：US18346622

申请日：2023-07-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Yan-Ting Lin ,  Clement Hsingjen Wann

IPC: H01L21/762 ,  H01L21/3115 ,  H01L21/02 ,  H01L29/66 ,  H01L27/12 ,  H01L29/06 ,  H01L27/092 ,  H01L29/36 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/31155 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/02321 ,  H01L21/02326 ,  H01L21/02337 ,  H01L29/66795 ,  H01L21/76237 ,  H01L27/1211 ,  H01L29/0649 ,  H01L27/0924 ,  H01L29/36 ,  H01L29/7851 ,  H01L21/823431

Abstract: The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.

公开(公告)号：US11658230B2

公开(公告)日：2023-05-23

申请号：US17101546

申请日：2020-11-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hsiung Tsai ,  Ru-Shang Hsiao ,  Clement Hsingjen Wann

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/0206 ,  H01L21/02057 ,  H01L21/02068 ,  H01L21/3065 ,  H01L21/30604 ,  H01L29/66545 ,  H01L29/785 ,  H01L21/823418 ,  H01L29/66636

Abstract: A method for forming a semiconductor structure is provided. The method includes the following operations. A substrate is received. A fin structure is formed on the substrate, and a dielectric layer is formed over the fin structure. A sacrificial gate is formed over the substrate. A portion of the dielectric layer is exposed through the sacrificial gate. Recesses are formed in the fin structure at two sides of the sacrificial gate. A cleaning operation is performed with an HF-containing plasma. The HF-containing plasma includes HF and NH3.

公开(公告)号：US11329139B2

公开(公告)日：2022-05-10

申请号：US16514373

申请日：2019-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hsiung Tsai ,  Kuo-Feng Yu ,  Yu-Ming Lin ,  Clement Hsingjen Wann

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/266

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; depositing a first dielectric layer and a second dielectric layer over the substrate; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and performing a treatment by introducing a trap-repairing element into at least one of the gate spacer, the second dielectric layer, the surface and the LDD regions at a time before the forming of the source/drain regions or subsequent to the formation of the ILD layer.

公开(公告)号：US10943790B2

公开(公告)日：2021-03-09

申请号：US16391006

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Tsz-Mei Kwok

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/06 ,  H01L29/36 ,  H01L21/02 ,  H01L29/08 ,  H01L29/34

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In an embodiment, a method of manufacturing a semiconductor device may include providing a substrate having a recess; epitaxially forming a first layer including a doped semiconductor material within the recess; and epitaxially forming a second layer including an undoped semiconductor material over at least a portion of the recess.

公开(公告)号：US10269577B2

公开(公告)日：2019-04-23

申请号：US15351289

申请日：2016-11-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Tsz-Mei Kwok

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/06 ,  H01L29/36 ,  H01L21/02 ,  H01L29/08 ,  H01L29/34

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In an embodiment, a method of manufacturing a semiconductor device may include providing a substrate having a recess; epitaxially forming a first layer including a doped semiconductor material within the recess; and epitaxially forming a second layer including an undoped semiconductor material over at least a portion of the recess.

公开(公告)号：US10037920B2

公开(公告)日：2018-07-31

申请号：US15276475

申请日：2016-09-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Jian-An Ke

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/3115 ,  H01L21/308 ,  H01L21/311 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/823814 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/28008 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818

Abstract: A method of forming a semiconductor device includes receiving a substrate with a gate structure and forming a spacer layer over the substrate and the gate structure. The method further includes implanting carbon into the spacer layer at an angle tilted away from a first direction perpendicular to a top surface of the substrate, which increases etch resistance of the spacer layer on sidewalls of the gate structure. The method optionally includes implanting germanium into the spacer layer at the first direction, which decreases etch resistance of the spacer layer overlaying the gate structure and the substrate. The method further includes etching the spacer layer to expose the gate structure, resulting in a first portion of the spacer layer on the sidewalls of the gate structure. Due to increased etch resistance, the first portion of the spacer layer maintains its profile and thickness in subsequent fabrication processes.

公开(公告)号：US09991343B2

公开(公告)日：2018-06-05

申请号：US14632465

申请日：2015-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hsiung Tsai

IPC: H01L29/15 ,  H01L29/08 ,  H01L29/36 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: The present disclosure provides an LDD-free semiconductor structure including a semiconductor layer, a gate over the semiconductor layer and a regrowth region made of semiconductor material positioned in the semiconductor layer. The regrowth region forms a source region or a drain region of the LDD-free semiconductor structure. The gate includes a gate electrode layer laterally covered by a gate spacer. The regrowth region extends towards a region beneath the gate spacer and close to a plane extending along a junction of the gate spacer and the gate electrode layer. The present disclosure also provides a method for manufacturing an LDD-free semiconductor structure. The method includes forming a gate over a semiconductor layer, removing a portion of the semiconductor layer and obtaining a recess, and forming a regrowth region over the recess.

公开(公告)号：US09865732B2

公开(公告)日：2018-01-09

申请号：US15171322

申请日：2016-06-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun Hsiung Tsai ,  Su-Hao Liu ,  Chien-Tai Chan ,  King-Yuen Wong ,  Chien-Chang Su

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7834 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/66636

Abstract: An integrated circuit includes a gate electrode and spacers along sidewalls of the gate electrode. The integrated circuit further includes a source/drain (S/D) region adjacent to the gate electrode. The S/D region includes a diffusion barrier structure at least partially in a recess of the substrate. The diffusion barrier structure includes an epitaxial layer having a first region and a second region. The first region is thinner than the second region, and the first region is misaligned with respect to the sidewalls of the gate electrode. The S/D region includes a doped silicon-containing structure over the diffusion barrier structure. The first region of the diffusion barrier structure is configured to partially prevent dopants of the doped silicon-containing structure from diffusing into the substrate. The second region of the diffusion barrier structure is configured to substantially completely prevent the dopants of the doped silicon-containing structure from diffusing into the substrate.

公开(公告)号：US09721853B2

公开(公告)日：2017-08-01

申请号：US13892421

申请日：2013-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Ming-Te Chen

IPC: G01N3/00 ,  G01K7/01 ,  H01L21/66 ,  H01L21/67 ,  H01L21/324

CPC classification number: H01L22/12 ,  H01L21/324 ,  H01L21/67288 ,  H01L22/20 ,  H01L22/26

Abstract: A system and method for forming a semiconductor device is provided. The system may measure characteristics of the substrate to determine an amount of induced stress on the substrate. The measured characteristics may include warpage, reflectivity and/or crack information about the substrate. The induced stress may be determined, at least in part, based on the measured characteristics. The system may compare the induced stress on the substrate to a maximum intrinsic strength of the substrate and adjust an anneal for the substrate based on the comparison. The adjustment may reduce or limit breakage of the substrate during the anneal. The system may control at least one of a peak anneal temperature and a maximum anneal duration for an anneal unit, which may perform an anneal on the substrate. The measurements and control may be performed ex-situ or in-situ with the anneal.