公开(公告)号：US20230377994A1

公开(公告)日：2023-11-23

申请号：US18230020

申请日：2023-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chandrashekhar Prakash SAVANT ,  Chia-Ming Tsai ,  Ming-Te Chen ,  Tien-Wei Yu

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823842 ,  H01L27/092 ,  H01L21/823807

Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.

公开(公告)号：US09721853B2

公开(公告)日：2017-08-01

申请号：US13892421

申请日：2013-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Ming-Te Chen

IPC: G01N3/00 ,  G01K7/01 ,  H01L21/66 ,  H01L21/67 ,  H01L21/324

CPC classification number: H01L22/12 ,  H01L21/324 ,  H01L21/67288 ,  H01L22/20 ,  H01L22/26

Abstract: A system and method for forming a semiconductor device is provided. The system may measure characteristics of the substrate to determine an amount of induced stress on the substrate. The measured characteristics may include warpage, reflectivity and/or crack information about the substrate. The induced stress may be determined, at least in part, based on the measured characteristics. The system may compare the induced stress on the substrate to a maximum intrinsic strength of the substrate and adjust an anneal for the substrate based on the comparison. The adjustment may reduce or limit breakage of the substrate during the anneal. The system may control at least one of a peak anneal temperature and a maximum anneal duration for an anneal unit, which may perform an anneal on the substrate. The measurements and control may be performed ex-situ or in-situ with the anneal.

公开(公告)号：US09543438B2

公开(公告)日：2017-01-10

申请号：US14515311

申请日：2014-10-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Ming-Te Chen

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/265 ,  H01L29/165 ,  H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/02 ,  H01L21/324 ,  H01L21/285 ,  H01L29/167 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/665 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7851

Abstract: An embodiment is a method of manufacturing a semiconductor device, the method including forming a first gate over a substrate, forming a recess in the substrate adjacent the first gate, epitaxially forming a strained material stack in the recess, the strained material stack comprising at least three layers, each of the at least three layers comprising a dopant. The method further includes co-implanting the strained material stack with dopants comprising boron, germanium, indium, tin, or a combination thereof, forming a metal layer on the strained material stack, and annealing the metal layer and the strained material stack forming a metal-silicide layer.

Abstract translation: 一个实施例是制造半导体器件的方法，该方法包括在衬底上形成第一栅极，在邻近第一栅极的衬底中形成凹槽，在凹槽中外延形成应变材料堆叠，应变材料堆叠至少包括 三层，所述至少三层中的每一层包括掺杂剂。 该方法还包括将应变材料堆叠与包含硼，锗，铟，锡或其组合的掺杂剂共同植入，在应变材料堆叠上形成金属层，以及退火金属层和形成金属的应变材料堆叠 硅化物层。

公开(公告)号：US10858736B2

公开(公告)日：2020-12-08

申请号：US15371068

申请日：2016-12-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Yi Chuang ,  Hsing-Jui Lee ,  Ming-Te Chen

IPC: C23C16/455 ,  C30B25/14 ,  C23C16/458 ,  H01L21/02 ,  H01J37/32 ,  H01L21/314 ,  C30B31/16 ,  C23C16/46

Abstract: An atomic layer deposition apparatus includes a chamber including a plurality of regions; and a heating device respectively providing specific temperature ranges for the plurality of regions. By flowing precursor gases at different flow rates in the different regions, thin films can be simultaneously formed in the different regions having different film thicknesses.

公开(公告)号：US09267982B2

公开(公告)日：2016-02-23

申请号：US13764260

申请日：2013-02-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shao-Hua Wang ,  Ming-Te Chen ,  Sheng-Wei Lee

IPC: H01J37/00 ,  G01R31/26 ,  H01J37/30 ,  H01J37/317

CPC classification number: H01J37/3171 ,  C23C14/48 ,  G01R31/2607 ,  G01R31/3177 ,  G01R31/318552 ,  G01R31/318558 ,  G01R31/318572 ,  G01R31/318594 ,  H01J37/3007 ,  H01J2237/15 ,  H01J2237/30472 ,  H01J2237/31701

Abstract: A processing apparatus includes an end station configured to support thereon a workpiece, an ion beam generator and a scanning device. The ion beam generator is configured to generate an ion beam toward the end station. The scanning device is configured to scan the ion beam in a transverse scanning direction. The scanning device is configured to be disposed in a first path of the ion beam toward the end station and out of a second path of the ion beam toward the end station.

Abstract translation: 一种处理装置，包括被配置为在其上支撑工件的终端站，离子束发生器和扫描装置。 离子束发生器被配置为朝向终端站产生离子束。 扫描装置被配置为沿横向扫描方向扫描离子束。 扫描装置被配置为设置在离子束的第一路径中朝着终端站并离开离子束的第二路径朝向终端站。

公开(公告)号：US09209243B2

公开(公告)日：2015-12-08

申请号：US14621245

申请日：2015-02-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Yi Chuang ,  Ta-Hsiang Kung ,  Hsing-Jui Lee ,  Ming-Te Chen

IPC: H01L29/00 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224

Abstract: Embodiments of the disclosure include a shallow trench isolation (STI) structure and a method of forming the same. A trench is formed in a substrate. A silicon oxide and a silicon liner layer are formed on sidewalls and a bottom surface of the trench. A flowable silicon oxide material fills in the trench, is cured, and then is partially removed. Another silicon oxide is deposited in the trench to fill the trench. The STI structure in a fabricated device includes a bottom portion having silicon oxide and a top portion having additionally a silicon oxide liner and a silicon liner on the sidewalls.

公开(公告)号：US09196452B2

公开(公告)日：2015-11-24

申请号：US13790783

申请日：2013-03-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Jiun Lee ,  Cheng-Hung Hu ,  Yh-Hsiu Hsiao ,  Kan Hwa Chang ,  Ming-Te Chen

IPC: H01J37/08 ,  H01L21/265 ,  H01J37/317

CPC classification number: H01J37/08 ,  H01J37/3171 ,  H01L21/26506

Abstract: Methods and apparatus for a carbon ion source head. An ionization chamber is configured to receive a process gas containing carbon and a noble carrier gas; a cathode is disposed in the ionization chamber and configured to emit electrons in thermionic emission; a graphite coating is provided on at least a portion of the cathode; and an outlet on the ionization chamber is configured to output carbon ions. A method for ion implantation of carbon is disclosed. Additional alternative embodiments are disclosed.

Abstract translation: 碳离子源头的方法和装置。 电离室构造成​​接收含有碳和贵重载气的工艺气体; 阴极设置在电离室中并且被配置为以热电子发射发射电子; 在阴极的至少一部分上提供石墨涂层; 并且电离室上的出口构造成输出碳离子。 公开了一种离子注入碳的方法。 公开了另外的替代实施例。

公开(公告)号：US12142682B2

公开(公告)日：2024-11-12

申请号：US17390817

申请日：2021-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chandrashekhar Prakash Savant ,  Kin Shun Chong ,  Tien-Wei Yu ,  Chia-Ming Tsai ,  Ming-Te Chen

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

公开(公告)号：US09982338B2

公开(公告)日：2018-05-29

申请号：US15597377

申请日：2017-05-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsun-Jen Chan ,  Cheng-Hung Hu ,  Yi-Hann Chen ,  Kang Hua Chang ,  Ming-Te Chen

IPC: C23C14/54 ,  H01L21/677 ,  H01L21/67 ,  H01L21/265 ,  H01J37/317

CPC classification number: C23C14/54 ,  H01J37/3171 ,  H01J2237/31701 ,  H01L21/265 ,  H01L21/26593 ,  H01L21/67115 ,  H01L21/67201 ,  H01L21/67213 ,  H01L21/67745

Abstract: A system includes an implantation chamber; a warming chamber, wherein the warming chamber is outside of the implantation chamber and has a sidewall shared with the implantation chamber; a first robotic arm configured to move a first wafer from the implantation chamber into the warming chamber; and a second robotic arm configured to move a second wafer into the implantation chamber.

公开(公告)号：US20170117277A1

公开(公告)日：2017-04-27

申请号：US15397203

申请日：2017-01-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Ming-Te Chen

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/324 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/401 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: An embodiment is a method of manufacturing a semiconductor device, the method including forming a first gate over a substrate, forming a recess in the substrate adjacent the first gate, epitaxially forming a strained material stack in the recess, the strained material stack comprising at least three layers, each of the at least three layers comprising a dopant. The method further includes co-implanting the strained material stack with dopants comprising boron, germanium, indium, tin, or a combination thereof, forming a metal layer on the strained material stack, and annealing the metal layer and the strained material stack forming a metal-silicide layer.