公开(公告)号：US11996361B2

公开(公告)日：2024-05-28

申请号：US17885026

申请日：2022-08-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shu-Cheng Chin ,  Yao-Min Liu ,  Hung-Wen Su ,  Chih-Chien Chi ,  Chi-Feng Lin

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L29/417 ,  H01L29/45 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76883 ,  H01L23/5283 ,  H01L29/41725 ,  H01L29/456 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266

摘要： A method of making a semiconductor device includes etching an insulating layer to form a first opening and a second opening. The method further includes depositing a conductive material in the first opening. The method further includes performing a surface modification process on the conductive material. The method further includes depositing, after the surface modification process, a first liner layer in the second opening, wherein the first liner layer extends over the conductive material and the insulating layer. The method further includes depositing a conductive fill over the first liner layer, wherein the conductive fill includes a different material from the conductive material.

公开(公告)号：US11345991B2

公开(公告)日：2022-05-31

申请号：US16509775

申请日：2019-07-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jen-Chun Wang ,  Ya-Lien Lee ,  Chih-Chien Chi ,  Hung-Wen Su

IPC分类号： C23C14/35 ,  H01L21/768 ,  H01J37/34 ,  C23C14/00 ,  C23C16/34 ,  C23C16/455 ,  C23C14/06 ,  C23C14/22 ,  H01L21/02 ,  H01L21/67 ,  C23C14/34 ,  H01L21/285 ,  C23C14/04 ,  C23C16/04 ,  H01L21/3205 ,  H01L23/532

摘要： A semiconductor device is manufactured by modifying an electromagnetic field within a deposition chamber. In embodiments in which the deposition process is a sputtering process, the electromagnetic field may be modified by adjusting a distance between a first coil and a mounting platform. In other embodiments, the electromagnetic field may be adjusted by applying or removing power from additional coils that are also present.

公开(公告)号：US10508356B2

公开(公告)日：2019-12-17

申请号：US15366195

申请日：2016-12-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Yuan Kao ,  Hung-Wen Su ,  Minghsing Tsai

IPC分类号： C25D21/12 ,  C25D21/10 ,  C25D17/00 ,  C25D7/12

摘要： A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.

公开(公告)号：US10199500B2

公开(公告)日：2019-02-05

申请号：US15226233

申请日：2016-08-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yao-Jen Chang ,  Chih-Chien Chi ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Kai-Shiang Kuo ,  Po-Cheng Shih ,  Jun-Yi Ruan

IPC分类号： H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/8238 ,  H01L27/092

摘要： A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

公开(公告)号：US20170170292A1

公开(公告)日：2017-06-15

申请号：US14969213

申请日：2015-12-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiao-Ping Liu ,  Hung-Chang Hsu ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Rueijer Lin ,  Sheng-Hsuan Lin ,  Syun-Ming Jang ,  Ya-Lien Lee ,  Yen-Shou Kao

IPC分类号： H01L29/66 ,  H01L29/423

CPC分类号： H01L21/823475 ,  H01L21/3083 ,  H01L21/823425 ,  H01L29/41783 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/78

摘要： A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack over a substrate. The first gate stack includes a gate electrode, a first hard mask (HM) disposed over the gate electrode, and sidewall spacers along sidewalls of the first gate stack. The method also includes forming a first dielectric layer over the first gate stack, forming a second HM over the first HM and top surfaces of sidewall spacers, forming a second dielectric layer over the second HM and the first dielectric layer and removing the second and first dielectric layers to form a trench to expose a portion of the substrate while the second HM is disposed over the first gate stack.

公开(公告)号：US20160260665A1

公开(公告)日：2016-09-08

申请号：US15156991

申请日：2016-05-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chien Chi ,  Hung-Wen Su

IPC分类号： H01L23/528 ,  H01L21/311 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/02271 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A representative semiconductor device includes a first dielectric layer overlying a substrate, at least a first opening in the first dielectric layer, a conformal dense layer lining the at least first opening in the first dielectric layer, a barrier layer overlying the conformal dense layer, a conductive feature in the at least first opening, where a portion of the first dielectric layer between any two adjacent conductive features is removed to form a second opening, the second opening exposing the conformal dense layer between the two adjacent conductive features, and a second dielectric layer having an air gap formed therein, the second dielectric layer disposed between the two adjacent conductive features.

摘要翻译： 代表性的半导体器件包括覆盖衬底的第一电介质层，第一电介质层中的至少第一开口，衬在第一电介质层中的至少第一开口的保形致密层，覆盖保形致密层的阻挡层， 在所述至少第一开口中的导电特征，其中去除任何两个相邻导电特征之间的所述第一介电层的一部分以形成第二开口，所述第二开口暴露所述两个相邻导电特征之间的所述共形致密层，以及第二电介质 层，其中形成有气隙，第二介电层设置在两个相邻的导电特征之间。

公开(公告)号：US20160111327A1

公开(公告)日：2016-04-21

申请号：US14879992

申请日：2015-10-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ya-Lien Lee ,  Hung-Wen Su ,  Kuei-Pin Lee ,  Yu-Hung Lin ,  Yu-Min Chang

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/28562 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76879 ,  H01L23/50 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating an integrated circuit includes depositing a cap layer on a substrate; depositing a dielectric layer on the cap layer; and forming a trench in the dielectric layer. The method further includes depositing a tantalum nitride (TaN) layer on a sidewall of the trench such that the TaN layer has a greater concentration of nitrogen than tantalum. The method further includes depositing a tantalum (Ta) layer on the TaN layer using physical vapor deposition (PVD); and depositing a metal layer over the Ta layer.

摘要翻译： 一种制造集成电路的方法包括在衬底上沉积覆盖层; 在所述盖层上沉积介电层; 并在介电层中形成沟槽。 该方法还包括在沟槽的侧壁上沉积氮化钽（TaN）层，使得TaN层具有比钽更高的氮浓度。 该方法还包括使用物理气相沉积（PVD）在TaN层上沉积钽（Ta）层; 并在Ta层上沉积金属层。

公开(公告)号：US09240378B2

公开(公告)日：2016-01-19

申请号：US14279360

申请日：2014-05-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Ken-Yu Chang ,  Hung-Wen Su

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/285

CPC分类号： H01L23/5226 ,  C23C14/046 ,  C23C14/165 ,  C23C14/345 ,  C23C14/35 ,  H01L21/2855 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1.

摘要翻译： 一种形成半导体结构的方法包括以下步骤：提供衬底; 在衬底上形成电介质; 形成凹陷在所述电介质的顶表面下方的开口; 在所述开口的侧壁上形成阻挡层; 进行物理气相沉积（PVD）以在阻挡层上形成铜层，所述开口的角部以预定的重新溅射比与顶表面和顶表面相交，使得铜层的厚度比 阻挡层和顶部表面上的铜层的厚度基本上大于1。

公开(公告)号：US09214383B2

公开(公告)日：2015-12-15

申请号：US13745060

申请日：2013-01-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wen-Jiun Liu ,  Chien-An Chen ,  Ya-Lien Lee ,  Hung-Wen Su ,  Minghsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L23/48 ,  H01L21/00 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/768 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned adhesion layer is formed on the substrate. A metal layer is deposited on the patterned adhesion layer. An elevated temperature thermal process is applied to agglomerate the metal layer to form a self-forming-metal-feature (SFMF) and a dielectric layer is deposited between SFMFs.

摘要翻译： 公开了制造半导体集成电路（IC）的方法。 该方法包括提供基板。 在基板上形成有图案的粘合层。 金属层沉积在图案化的粘合层上。 施加高温热处理以使金属层附聚以形成自形成金属特征（SFMF），并且介电层沉积在SFMF之间。

公开(公告)号：US09209073B2

公开(公告)日：2015-12-08

申请号：US13849608

申请日：2013-03-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Liang-Yueh Ou Yang ,  Chih-Yi Chang ,  Chen-Yuan Kao ,  Hung-Wen Su

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/288 ,  H01L21/32134 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76898 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/00

摘要： Presented herein is a method for electrolessly forming a metal cap in a via opening, comprising bringing a via into contact with metal solution, the via disposed in an opening in a substrate, and forming a metal cap in the opening and in contact with the via, the metal cap formed by an electroless chemical reaction. A metal solution may be applied to the via to form the metal cap. The metal solution may comprises at least cobalt and the cap may comprise at least cobalt, and may optionally further comprise tungsten, and wherein the forming the cap comprises forming the cap to further comprise at least tungsten. The metal solution may further comprise at least hypophosphite or dimethylaminoborane.

摘要翻译： 这里提出的是在通孔开口中无电地形成金属盖的方法，包括使通孔与金属溶液接触，通孔设置在基板的开口中，并且在开口中形成金属盖并与通孔 ，金属帽由无电化学反应形成。 可以将金属溶液施加到通孔以形成金属盖。 金属溶液可以包括至少钴，并且帽可以包含至少钴，并且可以任选地进一步包含钨，并且其中形成帽包括形成帽以进一步包含至少钨。 金属溶液还可以包含至少次磷酸盐或二甲基氨基硼烷。