公开(公告)号：US12252783B2

公开(公告)日：2025-03-18

申请号：US17444585

申请日：2021-08-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pin-Wen Chen ,  Yuan-Chen Hsu ,  Ken-Yu Chang

IPC: C23C16/14 ,  C23C16/52 ,  H01L21/28 ,  H01L21/285 ,  H01L29/40 ,  H01L29/66

Abstract: Low-flow tungsten chemical vapor deposition (CVD) techniques described herein provide substantially uniform deposition of tungsten on a semiconductor substrate. In some implementations, a flow of a processing vapor is provided to a CVD processing chamber such that a flow rate of tungsten hexafluoride in the processing vapor results in the tungsten layer being grown at a slower rate than a higher flow rate of the tungsten hexafluoride to promote substantially uniform growth of the tungsten layer. In this way, the low-flow tungsten CVD techniques may be used to achieve similar surface uniformity performance to an atomic layer deposition (ALD) while being a faster deposition process relative to ALD (e.g., due to the lower deposition rate and large quantity of alternating processing cycles of ALD). This reduces the likelihood of defect formation in the tungsten layer while increasing the throughput of semiconductor device processing for the semiconductor substrate (and other semiconductor substrates).

公开(公告)号：US20190273042A1

公开(公告)日：2019-09-05

申请号：US15909777

申请日：2018-03-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Wen Cheng ,  Wei-Yip Loh ,  Yu-Hsiang Liao ,  Sheng-Hsuan Lin ,  Hong-Mao Lee ,  Chun-I Tsai ,  Ken-Yu Chang ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L23/522 ,  H01L21/48 ,  H01L21/768 ,  H01L21/285 ,  H01L21/8238 ,  H01L23/498 ,  H01L23/00 ,  H01L29/66

Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region. Finally, a surface treatment can be performed in the contact region to form N-rich areas in the dielectric layer and a nitridation region in the substrate, and an adhesion layer can formed in the contact region to cover the side portions and the bottom portion of the contact region.

公开(公告)号：US09240378B2

公开(公告)日：2016-01-19

申请号：US14279360

申请日：2014-05-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ken-Yu Chang ,  Hung-Wen Su

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/285

CPC classification number: H01L23/5226 ,  C23C14/046 ,  C23C14/165 ,  C23C14/345 ,  C23C14/35 ,  H01L21/2855 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1.

Abstract translation: 一种形成半导体结构的方法包括以下步骤：提供衬底; 在衬底上形成电介质; 形成凹陷在所述电介质的顶表面下方的开口; 在所述开口的侧壁上形成阻挡层; 进行物理气相沉积（PVD）以在阻挡层上形成铜层，所述开口的角部以预定的重新溅射比与顶表面和顶表面相交，使得铜层的厚度比 阻挡层和顶部表面上的铜层的厚度基本上大于1。

公开(公告)号：US11062941B2

公开(公告)日：2021-07-13

申请号：US16806931

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ken-Yu Chang ,  Chun-I Tsai ,  Ming-Hsing Tsai ,  Wei-Jung Lin

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/67

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

公开(公告)号：US20200020578A1

公开(公告)日：2020-01-16

申请号：US16032416

申请日：2018-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ken-Yu Chang ,  Chun-I Tsai ,  Ming-Hsing Tsai ,  Wei-Jung Lin

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/67

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

公开(公告)号：US09437485B2

公开(公告)日：2016-09-06

申请号：US14245085

申请日：2014-04-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Cheng Kuo ,  Tzu-Chun Lo ,  Ming-Hsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

IPC: H01L21/4763 ,  H01L21/768 ,  G06F17/50 ,  H01L23/522

CPC classification number: H01L21/76838 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.

Abstract translation: 在本公开中描述了用于改善密集到隔离图案转移区域附近的处理窗口的半导体集成电路线结构和在布局处理中实现线结构的技术。 所公开的结构包括半导体衬底和衬底上方的材料层。 材料层具有紧密间隔的密集线结构，紧密密集线结构旁边的隔离线结构，以及形成在密集线附近和隔离线结构处的虚拟线肩结构。 虚拟线肩结构的一端连接到隔离线结构，另一端以基本垂直于隔离线结构的方向远离隔离线结构延伸。

公开(公告)号：US11817384B2

公开(公告)日：2023-11-14

申请号：US17567525

申请日：2022-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shuen-Shin Liang ,  Ken-Yu Chang ,  Hung-Yi Huang ,  Chien Chang ,  Chi-Hung Chuang ,  Kai-Yi Chu ,  Chun-I Tsai ,  Chun-Hsien Huang ,  Chih-Wei Chang ,  Hsu-Kai Chang ,  Chia-Hung Chu ,  Keng-Chu Lin ,  Sung-Li Wang

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5228

Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a bottom metal line in a first interlayer dielectric layer, forming a second interlayer dielectric layer over the bottom metal line, exposing a top surface of the bottom metal line, increasing a total surface area of the exposed top surface of the bottom metal line, forming a conductive via over the bottom metal line, and forming a top metal line over the conductive via.

公开(公告)号：US11217524B1

公开(公告)日：2022-01-04

申请号：US16900622

申请日：2020-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shuen-Shin Liang ,  Ken-Yu Chang ,  Hung-Yi Huang ,  Chien Chang ,  Chi-Hung Chuang ,  Kai-Yi Chu ,  Chun-I Tsai ,  Chun-Hsien Huang ,  Chih-Wei Chang ,  Hsu-Kai Chang ,  Chia-Hung Chu ,  Keng-Chu Lin ,  Sung-Li Wang

IPC: H01L23/522 ,  H01L21/768

Abstract: The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal.

公开(公告)号：US10580693B2

公开(公告)日：2020-03-03

申请号：US16032416

申请日：2018-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ken-Yu Chang ,  Chun-I Tsai ,  Ming-Hsing Tsai ,  Wei-Jung Lin

IPC: H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/67

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

公开(公告)号：US20140208283A1

公开(公告)日：2014-07-24

申请号：US14245085

申请日：2014-04-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Cheng Kuo ,  Tzu-Chun Lo ,  Ming-Hsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

IPC: H01L21/768 ,  G06F17/50

CPC classification number: H01L21/76838 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.

Abstract translation: 在本公开中描述了用于改善密集到隔离图案转移区域附近的处理窗口的半导体集成电路线结构和在布局处理中实现线结构的技术。 所公开的结构包括半导体衬底和衬底上方的材料层。 材料层具有紧密间隔的密集线结构，紧密密集线结构旁边的隔离线结构，以及形成在密集线附近和隔离线结构处的虚拟线肩结构。 虚拟线肩结构的一端连接到隔离线结构，另一端以基本垂直于隔离线结构的方向远离隔离线结构延伸。