公开(公告)号：US20240355742A1

公开(公告)日：2024-10-24

申请号：US18760471

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Wei Chang ,  Chien-Shun Liao ,  Sung-Li Wang ,  Shuen-Shin Liang ,  Shu-Lan Chang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Hsu-Kai Chang

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53266 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/53238

Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

公开(公告)号：US20190214296A1

公开(公告)日：2019-07-11

申请号：US16354362

申请日：2019-03-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Shuen-Shin Liang ,  Jung-Hao Chang ,  Chia-Hung Chu ,  Keng-Chu Lin

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76883

Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.

公开(公告)号：US12009294B2

公开(公告)日：2024-06-11

申请号：US17875533

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Wei Chang ,  Sung-Li Wang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Fang-Wei Lee

IPC: H01L23/522 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53266

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

公开(公告)号：US09762052B2

公开(公告)日：2017-09-12

申请号：US14015945

申请日：2013-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Hung Chu ,  Kuo-Ji Chen

IPC: H02H9/00 ,  H02H9/04

CPC classification number: H02H9/046

Abstract: A device includes a first power node, a second power node, a first input node, a second input node, a protected circuit, and a switch circuit. The protected circuit is coupled between the first power node and the second power node, and the protected circuit is further coupled with the second input node. The switch circuit is coupled with the first power node, the second power node, the first input node, and the second input node. The switch circuit is configured to electrically decouple the first input node and the second input node after (a) the first power node is floating or electrically coupled to the second power node and (b) a voltage level at the first input node is greater than a voltage level at the second power node by a predetermined voltage value.

公开(公告)号：US20150079806A1

公开(公告)日：2015-03-19

申请号：US14029226

申请日：2013-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Hsien Hsu ,  Hong-Hsing Chou ,  Hu-Wei Lin ,  Chi-Jen Hsieh ,  Jr-Wei Ye ,  Yuan-Ting Huang ,  Ching-Hsing Chiang ,  Hua-Kuang Teng ,  Yen-Chen Lin ,  Carolina Poe ,  Tsung-Cheng Huang ,  Chia-Hung Chu

IPC: H01L21/02

CPC classification number: G03F7/162 ,  B05D1/005 ,  H01L21/6715

Abstract: A method includes rotating a wafer at a first speed for a first time duration. The wafer is rotated at a second speed that is lower than the first speed for a second time duration after the first time duration. The wafer is rotated at a third speed that is higher than the second speed for a third time duration after the second time duration. A photoresist is dispensed on the wafer during the first time duration and at least a portion of a time interval that includes the second time duration and the third time duration.

Abstract translation: 一种方法包括以第一速度第一时间旋转晶片。 在第一持续时间之后，晶片以低于第一速度的第二速度旋转第二持续时间。 在第二持续时间之后，晶片以比第二速度高三秒的速度旋转第三持续时间。 在第一时间期间和包括第二持续时间和第三持续时间的时间间隔的至少一部分中，在晶片上分配光致抗蚀剂。

公开(公告)号：US12170331B2

公开(公告)日：2024-12-17

申请号：US17651314

申请日：2022-02-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Wei Chang ,  Chia-Hung Chu ,  Hsu-Kai Chang ,  Sung-Li Wang ,  Kuan-Kan Hu ,  Shuen-Shin Liang ,  Kao-Feng Lin ,  Hung Pin Lu ,  Yi-Ying Liu ,  Chuan-Hui Shen

IPC: H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L29/40 ,  H01L29/417

Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.

公开(公告)号：US20240339497A1

公开(公告)日：2024-10-10

申请号：US18747151

申请日：2024-06-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Wei Chang ,  Shuen-Shin Liang ,  Sung-Li Wang ,  Hsu-Kai Chang ,  Chia-Hung Chu ,  Chien-Shun Liao ,  Yi-Ying Liu

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/1033 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.

公开(公告)号：US20240021687A1

公开(公告)日：2024-01-18

申请号：US18191750

申请日：2023-03-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Wei Chang ,  Chien Chang ,  Kan-Ju Lin ,  Harry Chien ,  Shuen-Shin Liang ,  Chia-Hung Chu ,  Sung-Li Wang ,  Shahaji B. More ,  Yueh-Ching Pai

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/41791 ,  H01L27/0886 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823418

Abstract: A source/drain component is disposed over an active region and surrounded by a dielectric material. A source/drain contact is disposed over the source/drain component. The source/drain contact includes a conductive capping layer and a conductive material having a different material composition than the conductive capping layer. The conductive material has a recessed bottom surface that is in direct contact with the conductive capping layer. A source/drain via is disposed over the source/drain contact. The source/drain via and the conductive material have different material compositions. The conductive capping layer contains tungsten, the conductive material contains molybdenum, and the source/drain via contains tungsten.

公开(公告)号：US20170012038A1

公开(公告)日：2017-01-12

申请号：US15273187

申请日：2016-09-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hui Chen ,  Chia-Hung Chu ,  Kuo-Ji Chen ,  Ming-Hsiang Song ,  Lee-Chung Lu

IPC: H01L27/02 ,  H03K19/003 ,  H03K19/0175

CPC classification number: H02H9/046 ,  H01L27/0248 ,  H01L27/0266 ,  H01L27/0285 ,  H03K3/013 ,  H03K5/003 ,  H03K19/003 ,  H03K19/017509

Abstract: In some embodiments, a method includes providing an input voltage to a level-shifting circuit, where the input voltage is in a first power domain, shifting the input voltage to an output voltage using the level-shifting circuit, where the output voltage is in a second power domain different from the first power domain, and where the level-shifting circuit is coupled to power supply voltages in the second power domain. The method further includes in response to an electrostatic discharge (ESD) event, turning off a first transistor coupled between a first node of the level-shifting circuit and a reference low voltage level of the second power domain.

Abstract translation: 在一些实施例中，一种方法包括向电平移位电路提供输入电压，其中输入电压处于第一功率域，使用电平移位电路将输入电压移动到输出电压，其中输出电压处于 与第一功率域不同的第二功率域，以及其中电平移动电路耦合到第二电源域中的电源电压。 该方法还包括响应于静电放电（ESD）事件，关闭耦合在电平移位电路的第一节点和第二电源域的参考低电压电平之间的第一晶体管。

公开(公告)号：US20240282698A1

公开(公告)日：2024-08-22

申请号：US18650166

申请日：2024-04-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Wei Chang ,  Sung-Li Wang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Fang-Wei Lee

IPC: H01L23/522 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53266

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.