公开(公告)号：US10755934B2

公开(公告)日：2020-08-25

申请号：US16711349

申请日：2019-12-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Chi-Jen Liu ,  Ying-Liang Chuang ,  Li-Chieh Wu ,  Liang-Guang Chen ,  Ming-Liang Yen

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  B24B37/20 ,  H01L21/321 ,  H01L21/67

Abstract: A chemical mechanical polishing (CMP) system and associated semiconductor fabrication methods are disclosed herein. An exemplary method includes performing a planarization process in a polishing unit of a CMP system to planarize a surface of a material layer using a CMP slurry. The method further includes, after performing the planarization process, performing a buffing process in the polishing unit of the CMP system to buff the surface of the material layer using an ozone gas dissolved in deionized water (O3/DIW) solution. The method further includes controlling the performing of the planarization process and the performing of the buffing process, such that the CMP slurry is received by the polishing unit from a first pipeline during the planarization process and the O3/DIW solution is received by the polishing unit from a second pipeline during the buffing process.

公开(公告)号：US20180350675A1

公开(公告)日：2018-12-06

申请号：US16050168

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hao Chung ,  Chang-Sheng Lin ,  Kuo-Feng Huang ,  Li-Chieh Wu ,  Chun-Chieh Lin

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76883 ,  H01L21/02074 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/535

Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

公开(公告)号：US20160064518A1

公开(公告)日：2016-03-03

申请号：US14937301

申请日：2015-11-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Jen Liu ,  Li-Chieh Wu ,  Liang-Guang Chen ,  Shich-Chang Suen

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/321 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/02074 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76895 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A method includes forming a dummy gate of a transistor at a surface of a wafer, removing the dummy gate, and filling a metallic material into a trench left by the removed dummy gate. A Chemical Mechanical Polish (CMP) is then performed on the metallic material, wherein a remaining portion of the metallic material forms a metal gate of the transistor. After the CMP, a treatment is performed on an exposed top surface of the metal gate using an oxidation-and-etching agent comprising chlorine and oxygen.

公开(公告)号：US20210391186A1

公开(公告)日：2021-12-16

申请号：US16902180

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD

Inventor： Ji Cui ,  Fu-Ming Huang ,  Ting-Kui Chang ,  Tang-Kuei Chang ,  Chun-Chieh Lin ,  Wei-Wei Liang ,  Liang-Guang Chen ,  Kei-Wei Chen ,  Hung Yen ,  Ting-Hsun Chang ,  Chi-Hsiang Shen ,  Li-Chieh Wu ,  Chi-Jen Liu

IPC: H01L21/321 ,  B24B37/04 ,  B24B37/10 ,  C09G1/02

Abstract: A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.

公开(公告)号：US10957587B2

公开(公告)日：2021-03-23

申请号：US16450665

申请日：2019-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Chieh Wu ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Tang-Kuei Chang ,  Chia Hsuan Lee ,  Jian-Ci Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/321 ,  C09G1/04 ,  H01L23/532 ,  H01L23/535

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a conductive feature over a semiconductor substrate and forming a dielectric layer over the conductive feature. The method also includes forming an opening in the dielectric layer to expose the conductive feature. The method further includes forming a conductive material to overfill the opening. In addition, the method includes thinning the conductive material using a chemical mechanical polishing process. A slurry used in the chemical mechanical polishing process includes an iron-containing oxidizer that oxidizes a portion of the conductive material.

公开(公告)号：US20200051855A1

公开(公告)日：2020-02-13

申请号：US16655509

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hao Chung ,  Chang-Sheng Lin ,  Kuo-Feng Huang ,  Li-Chieh Wu ,  Chun-Chieh Lin

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/02

Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

公开(公告)号：US10109523B2

公开(公告)日：2018-10-23

申请号：US15395057

申请日：2016-12-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hao Chung ,  Chang-Sheng Lin ,  Kuo-Feng Huang ,  Li-Chieh Wu ,  Chun-Chieh Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/535

Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

公开(公告)号：US20170125549A1

公开(公告)日：2017-05-04

申请号：US15407784

申请日：2017-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Jen Liu ,  Li-Chieh Wu ,  Liang-Guang Chen ,  Shich-Chang Suen

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L29/66545 ,  H01L21/02074 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76895 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A method includes forming a dummy gate of a transistor at a surface of a wafer, removing the dummy gate, and filling a metallic material into a trench left by the removed dummy gate. A Chemical Mechanical Polish (CMP) is then performed on the metallic material, wherein a remaining portion of the metallic material forms a metal gate of the transistor. After the CMP, a treatment is performed on an exposed top surface of the metal gate using an oxidation-and-etching agent comprising chlorine and oxygen.

公开(公告)号：US09269585B2

公开(公告)日：2016-02-23

申请号：US14152497

申请日：2014-01-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02068 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/28079 ,  H01L21/28132 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L29/401 ,  H01L29/66545

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract translation: 本公开提供了一种用于形成集成电路（IC）结构的方法。 该方法包括提供金属栅极（MG），形成在MG上的蚀刻停止层（ESL）以及形成在ESL上的电介质层。 该方法还包括蚀刻ESL和介电层以形成沟槽。 暴露在沟槽中的MG的表面被氧化以在MG上形成第一氧化物层。 该方法还包括使用H 3 PO 4溶液去除第一氧化物层。

公开(公告)号：US20150072511A1

公开(公告)日：2015-03-12

申请号：US14024247

申请日：2013-09-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Jen Liu ,  Li-Chieh Wu ,  Shich-Chang Suen ,  Liang-Guang Chen

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/306

CPC classification number: H01L29/66545 ,  H01L21/02074 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76895 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A method includes forming a dummy gate of a transistor at a surface of a wafer, removing the dummy gate, and filling a metallic material into a trench left by the removed dummy gate. A Chemical Mechanical Polish (CMP) is then performed on the metallic material, wherein a remaining portion of the metallic material forms a metal gate of the transistor. After the CMP, a treatment is performed on an exposed top surface of the metal gate using an oxidation-and-etching agent comprising chlorine and oxygen.

Abstract translation: 一种方法包括在晶片的表面上形成晶体管的虚拟栅极，去除虚拟栅极，并将金属材料填充到由去除的虚拟栅极留下的沟槽中。 然后对金属材料进行化学机械抛光（CMP），其中金属材料的剩余部分形成晶体管的金属栅极。 在CMP之后，使用包含氯和氧的氧化 - 蚀刻剂在金属栅极的暴露的顶表面上进行处理。