公开(公告)号：US11335593B2

公开(公告)日：2022-05-17

申请号：US16787891

申请日：2020-02-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Bo-Jhih Shen ,  Yi-Wei Chiu ,  Hung Jui Chang

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L21/285

摘要： Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature.

公开(公告)号：US11171003B2

公开(公告)日：2021-11-09

申请号：US16204023

申请日：2018-11-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Teng Liao ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Li-Te Hsu

IPC分类号： H01L21/8238 ,  H01L21/225 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

摘要： A method includes etching a semiconductor substrate to form a first trench and a second trench. A remaining portion of the semiconductor substrate is left between the first trench and the second trench as a semiconductor region. A doped dielectric layer is formed on sidewalls of the semiconductor region and over a top surface of the semiconductor region. The doped dielectric layer includes a dopant. The first trench and the second trench are filled with a dielectric material. An anneal is then performed, and a p-type dopant or an n-type dopant in the doped dielectric layer is diffused into the semiconductor region to form a diffused semiconductor region.

公开(公告)号：US11043427B2

公开(公告)日：2021-06-22

申请号：US16665474

申请日：2019-10-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC分类号： H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/3213 ,  H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311

摘要： A semiconductor device and method of manufacture are provided in which an the physical characteristics of a dielectric material are modified in order to provide additional benefits to surrounding structures during further processing. The modification may be performed by implanting ions into the dielectric material to form a modified region. Once the ions have been implanted, further processing relies upon the modified structure of the modified region instead of the original structure.

公开(公告)号：US11043251B2

公开(公告)日：2021-06-22

申请号：US16565640

申请日：2019-09-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Bo-Jhih Shen ,  Kuang-I Liu ,  Joung-Wei Liou ,  Jinn-Kwei Liang ,  Yi-Wei Chiu ,  Chin-Hsing Lin ,  Li-Te Hsu ,  Han-Ting Tsai ,  Cheng-Yi Wu ,  Shih-Ho Lin

IPC分类号： H01L21/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  G11B5/39 ,  G01R33/09

摘要： A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

公开(公告)号：US20190244849A1

公开(公告)日：2019-08-08

申请号：US16266797

申请日：2019-02-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chin-Huei Chiu ,  Tsung Fan Yin ,  Chen-Yi Liu ,  Hua-Li Hung ,  Xi-Zong Chen ,  Yi-Wei Chiu

IPC分类号： H01L21/683 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/67 ,  H01L29/78 ,  H01L21/768 ,  H01L21/687

CPC分类号： H01L21/6833 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/67069 ,  H01L21/67103 ,  H01L21/6831 ,  H01L21/68735 ,  H01L21/768 ,  H01L29/66545 ,  H01L29/785

摘要： Etch uniformity is improved by providing a thermal pad between an insert ring and electrostatic chuck in an etching chamber. The thermal pad provides a continuous passive heat path to dissipate heat from the insert ring and wafer edge to the electrostatic chuck. The thermal pad helps to keep the temperature of the various components in contact with or near the wafer at a more consistent temperature. Because temperature may affect etch rate, such as with etching hard masks over dummy gate formations, a more consistent etch rate is attained. The thermal pad also provides for etch rate uniformity across the whole wafer and not just at the edge. The thermal pad may be used in an etch process to perform gate replacement by removing hard mask layer(s) over a dummy gate electrode.

公开(公告)号：US10269624B2

公开(公告)日：2019-04-23

申请号：US15801154

申请日：2017-11-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Xi-Zong Chen ,  Y. H. Kuo ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/28 ,  H01L23/538 ,  H01L27/088 ,  H01L29/417 ,  H01L21/027

摘要： An embodiment method includes patterning an opening through a dielectric layer, depositing an adhesion layer along sidewalls and a bottom surface of the opening, depositing a first mask layer in the opening over the adhesion layer, etching back the first mask layer below a top surface of the dielectric layer, and widening an upper portion of the opening after etching back the first mask layer. The first mask layer masks a bottom portion of the opening while widening the upper portion of the opening. The method further includes removing the first mask layer after widening the upper portion of the opening and after removing the first mask layer, forming a contact in the opening by depositing a conductive material in the opening over the adhesion layer.

公开(公告)号：US20190006236A1

公开(公告)日：2019-01-03

申请号：US16045073

申请日：2018-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tsang Hsieh ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/475 ,  H01L23/528 ,  H01L21/4757 ,  H01L29/06

摘要： A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

公开(公告)号：US10163715B2

公开(公告)日：2018-12-25

申请号：US15789257

申请日：2017-10-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Wei Chiu ,  Ying Ting Hsia ,  Tzu-Chan Weng

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8238

摘要： A FinFET device and a method of forming the same are provided. A method includes forming a fin over a substrate. An isolation region is formed adjacent the fin. A dummy gate structure is formed over the fin. The fin adjacent the dummy gate structure is recessed to form a first recess. The first recess has a U-shaped bottom surface. The U-shaped bottom surface is below a top surface of the isolation region. The first recess is reshaped to form a reshaped first recess. The reshaped first recess has a V-shaped bottom surface. At least a portion of the V-shaped bottom surface comprises one or more steps. A source/drain region is epitaxially grown in the reshaped first recess.

公开(公告)号：US20180350947A1

公开(公告)日：2018-12-06

申请号：US16045175

申请日：2018-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Teng Liao ,  Yi-Wei Chiu ,  Xi-Zong Chen ,  Chia-Ching Tsai

IPC分类号： H01L29/66 ,  H01L21/321 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/28 ,  H01L23/528 ,  H01L23/485 ,  H01L21/768 ,  H01L29/423 ,  H01L29/165

CPC分类号： H01L29/66545 ,  H01L21/28123 ,  H01L21/32115 ,  H01L21/32137 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5283 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

摘要： A method includes forming a dummy gate stack over a semiconductor region, forming a gate spacer on a sidewall of the dummy gate stack, removing the dummy gate stack to form an opening, forming a replacement gate stack in the opening, recessing the replacement gate stack to form a recess, filling the recess with a conductive material, and performing a planarization to remove excess portions of the conductive material over the gate spacer. A remaining portion of the conductive material forms a gate contact plug. A top portion of the gate contact plug is at a same level as a top portion of the first gate spacer

公开(公告)号：US20180151353A1

公开(公告)日：2018-05-31

申请号：US15725744

申请日：2017-10-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： En-Ping Lin ,  Yi-Wei Chiu ,  Tzu-Chan Weng ,  Wen-Zhong Ho

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L21/302 ,  C23C16/40

CPC分类号： H01L21/02129 ,  C23C16/401 ,  H01L21/02008 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02389 ,  H01L21/302 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/6719 ,  H01L21/68757 ,  H01L21/76224 ,  H01L21/76243

摘要： A method includes etching a first oxide layer in a wafer. The etching is performed in an etcher having a top plate overlapping the wafer, and the top plate is formed of a non-oxygen-containing material. The method further includes etching a nitride layer underlying the first oxide layer in the etcher until a top surface of a second oxide layer underlying the nitride layer is exposed. The wafer is then removed from the etcher, with the top surface of the second oxide layer exposed when the wafer is removed.