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    THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    2.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20250008747A1

    公开(公告)日：2025-01-02

    申请号：US18537013

    申请日：2023-12-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Suhyun Bang ,  Seulji Song ,  Youngsun Song

    IPC: H10B63/00 ,  G11C5/06 ,  H10N70/00

    Abstract: A three-dimensional memory device includes a base insulating layer on a substrate, a stack structure including word lines and first interlayer insulating layers which are alternately stacked on the base insulating layer, and a second interlayer insulating layer on an uppermost one of the word lines, bit lines that are in the stack structure and spaced apart from each other in a first direction parallel to a top surface of the substrate, each bit line including a first portion that protrudes from a top surface of the stack structure and a second portion that are in the stack structure, an outer electrode on the stack structure and on the first portions of the bit lines, and a dielectric layer between the outer electrode and the first portion of the bit line and surrounding a side surface of the first portion of the bit line in plan view.

    VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    3.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210167130A1

    公开(公告)日：2021-06-03

    申请号：US16937963

    申请日：2020-07-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyusul PARK ,  Woohyun PARK ,  Ilmok PARK ,  Seulji Song

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A variable resistance memory device and a method of fabricating a variable resistance memory device, the device including first conductive lines extending in a first direction; second conductive lines extending in a second direction crossing the first direction; and memory cells at respective intersection points of the first conductive lines and the second conductive lines, wherein each of the memory cells includes a switching pattern, an intermediate electrode, a variable resistance pattern, and an upper electrode, which are between the first and second conductive lines and are connected in series; and a spacer structure including a first spacer and a second spacer, the first spacer being on a side surface of the upper electrode, and the second spacer covering the first spacer and a side surface of the variable resistance pattern such that the second spacer is in contact with the side surface of the variable resistance pattern.

    VERTICAL CHANNEL TRANSISTORS HAVE ENHANCED SOURCE-TO-DRAIN CURRENT PATHS THEREIN
    4.
    发明申请
    VERTICAL CHANNEL TRANSISTORS HAVE ENHANCED SOURCE-TO-DRAIN CURRENT PATHS THEREIN 有权

    公开(公告)号：US20250015135A1

    公开(公告)日：2025-01-09

    申请号：US18732958

    申请日：2024-06-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hwayeong Lee ,  Seulji Song

    IPC: H01L29/08 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H10B12/00

    Abstract: A vertical channel transistor includes a substrate having a bit line thereon, and a vertical channel layer including a first metal oxide, on the bit line. A lower insertion layer is provided, which extends between the bit line and a first end of the channel layer, and includes a second metal oxide having a greater bonding energy relative to the first metal oxide. A lower source/drain region is provided, which extends between the first end of the channel layer and the lower insertion layer, and includes a first metal dopant that is a reduced form of the first metal oxide. An upper source/drain region is provided, which is electrically connected to a second end of the channel layer, and includes the first metal dopant. An insulated gate line is provided on the channel layer.

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20240422994A1

    公开(公告)日：2024-12-19

    申请号：US18653689

    申请日：2024-05-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngsun Song ,  Seulji Song

    IPC: H10B63/00

    Abstract: A semiconductor memory device includes a first source line extending in a first horizontal direction, a second source line extending on the first source line in the first horizontal direction, a plurality of word line plates arranged apart from each other in a vertical direction, between the first source line and the second source line, a vertical bit line configured to penetrate the plurality of word line plates and extending in the vertical direction, a selector arranged between the plurality of word line plates and the vertical bit line, a first vertical channel transistor arranged between the vertical bit line and the first source line, and a second vertical channel transistor arranged between the vertical bit line and the second source line.

    Variable resistance memory device
    6.
    发明授权
    Variable resistance memory device 有权

    公开(公告)号：US11276821B2

    公开(公告)日：2022-03-15

    申请号：US16741936

    申请日：2020-01-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seulji Song ,  Jonguk Kim ,  Kyusul Park ,  Woohyun Park ,  Jonghyun Paek

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A semiconductor device includes a plurality of first conductive lines disposed on a substrate, a plurality of second conductive lines intersecting the plurality of first conductive lines, and a plurality of cell structures interposed between the plurality of first conductive lines and the plurality of second conductive lines. At least one among the plurality of cell structures includes a first electrode, a switching element disposed on the first electrode, a second electrode disposed on the switching element, a first metal pattern disposed on the second electrode, a variable resistance pattern interposed between the first metal pattern and at least one among the plurality of second conductive lines, and a first spacer disposed on a sidewall of the variable resistance pattern, a sidewall of the first metal pattern and a sidewall of the second electrode.

    MEMORY DEVICE INCLUDING SWITCHING PATTERN
    8.
    发明申请
    MEMORY DEVICE INCLUDING SWITCHING PATTERN 有权

    公开(公告)号：US20250056814A1

    公开(公告)日：2025-02-13

    申请号：US18796880

    申请日：2024-08-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seulji Song ,  Hodae Kim ,  Woojun Jeong

    IPC: H10B63/00 ,  H10N70/00

    Abstract: A memory device includes a first conductive line, a second conductive line, and a memory cell disposed between the first and second conductive lines. The memory cell includes a lower electrode layer, a switching pattern, and an upper electrode layer. The switching pattern includes a main region including a pair of first side walls and a pair of second walls, and a corner region at four corners of the main region. The switching pattern includes a chalcogenide layer including a Group VI chalcogen element, an element of Group IV and an element of Group V, and the concentration of the Group IV element in the corner region is greater than that of the Group IV element in the main region, or the concentration of the Group V element in the corner region is greater than that of the Group V element in the main region.

    SEMICONDUCTOR MEMORY DEVICES
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20250048655A1

    公开(公告)日：2025-02-06

    申请号：US18737537

    申请日：2024-06-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Bonjae KOO ,  Seulji Song ,  Youngsun Song

    IPC: H10B99/00

    Abstract: Provided is a semiconductor memory device including: cell blocks, each including a folding structure in which electrode structures and insulating structures are alternately provided, wherein the electrode structures and the insulating structures extend in a vertical direction and are connected with each other so as to have at least two U-shaped structures forming villus shapes in a plan view, the electrode structures include a vertical electrode and a switching material layer, and the cell blocks are provided in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction; and a gate stack structure including gate electrodes and interlayer insulating layers that are alternately stacked in the vertical direction along sidewalls of the electrode structures.

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