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公开(公告)号：US10930848B2
公开(公告)日：2021-02-23
申请号：US16415424
申请日：2019-05-17
发明人： Byongju Kim , Young-Min Ko , Jonguk Kim , Jaeho Jung , Dongsung Choi
摘要： A method of manufacturing a variable resistance memory device includes: forming an array of memory cells on a substrate, each memory cell including a variable resistance structure and a switching element; and forming a sidewall insulating layer covering a sidewall of the switching element. The forming the sidewall insulating layer includes: a preliminary step of supplying a silicon source to an exposed sidewall of the switching element; and a main step of performing a process cycle a plurality of times, the process cycle comprising supplying the silicon source and supplying a reaction gas, A time duration of the supplying the silicon source in the preliminary step is longer than a time duration of the supplying the silicon gas in the process cycle in the main step.
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公开(公告)号：US20220037401A1
公开(公告)日：2022-02-03
申请号：US17224303
申请日：2021-04-07
发明人： Jeonghee Park , Jonguk Kim , Byeongju Bae
摘要： A resistive memory device includes a plurality of first conductive lines in a first area and a second area on a substrate, a plurality of second conductive lines in the first area and the second area, the plurality of second conductive lines being apart from the plurality of first conductive lines in a vertical direction, and a plurality of memory cells connected to the first and second conductive lines at a plurality of intersections between the plurality of first and second conductive lines in the first area and the second area. The plurality of memory cells include an active memory cell in the first area and a dummy memory cell in the second area. The active memory cell including a first resistive memory pattern having a first width and the dummy memory cell including a second resistive memory pattern having a second width greater than the first width.
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公开(公告)号：US09893271B2
公开(公告)日：2018-02-13
申请号：US15210151
申请日：2016-07-14
发明人： Junghwan Park , Jonguk Kim , Soonoh Park , Jung Moo Lee , Sugwoo Jung
CPC分类号： H01L43/02 , H01L27/228 , H01L43/08 , H01L43/12
摘要： A semiconductor memory device includes a selection transistor on a semiconductor substrate, a lower contact plug connected to a drain region of the selection transistor, and a magnetic tunnel junction pattern on the lower contact plug, the magnetic tunnel junction pattern including a bottom electrode in contact with the lower contact plug, the bottom electrode being an amorphous tantalum nitride layer, a top electrode on the bottom electrode, first and second magnetic layers between the top and bottom electrodes, and a tunnel barrier layer between the first and second magnetic layers.
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公开(公告)号：US11456414B2
公开(公告)日：2022-09-27
申请号：US16416472
申请日：2019-05-20
发明人： Jonguk Kim , Young-Min Ko , Byongju Kim , Jaeho Jung , Dongsung Choi
摘要： A method of manufacturing a variable resistance memory device may include: forming a memory cell including a variable resistance pattern on a substrate; performing a first process to deposit a first protective layer covering the memory cell; and performing a second process to deposit a second protective layer on the first protective layer. The first process and the second process may use the same source material and the same nitrogen reaction material, and a nitrogen content in the first protective layer may be less than a nitrogen content in the second protective layer.
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公开(公告)号：US11276821B2
公开(公告)日：2022-03-15
申请号：US16741936
申请日：2020-01-14
发明人： Seulji Song , Jonguk Kim , Kyusul Park , Woohyun Park , Jonghyun Paek
摘要： A semiconductor device includes a plurality of first conductive lines disposed on a substrate, a plurality of second conductive lines intersecting the plurality of first conductive lines, and a plurality of cell structures interposed between the plurality of first conductive lines and the plurality of second conductive lines. At least one among the plurality of cell structures includes a first electrode, a switching element disposed on the first electrode, a second electrode disposed on the switching element, a first metal pattern disposed on the second electrode, a variable resistance pattern interposed between the first metal pattern and at least one among the plurality of second conductive lines, and a first spacer disposed on a sidewall of the variable resistance pattern, a sidewall of the first metal pattern and a sidewall of the second electrode.
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6.发明申请公开(公告)号：US20210050520A1
公开(公告)日：2021-02-18
申请号：US16874781
申请日：2020-05-15
发明人： Youngmin Ko , Jonguk Kim , Jaeho Jung , Dongsung Choi
摘要： A method for manufacturing a semiconductor device includes forming a first pattern structure having a first opening on a lower structure comprising a semiconductor substrate. The first pattern structure includes a stacked pattern and a first spacer layer covering at least a side surface of the stacked pattern. A first flowable material layer including a SiOCH material is formed on the first spacer layer to fill the first opening and cover an upper portion of the first pattern structure. A first curing process including supplying a gaseous ammonia catalyst into the first flowable material layer is performed on the first flowable material layer to form a first cured material layer that includes water. A second curing process is performed on the first cured material layer to form a first low-k dielectric material layer. The first low-k dielectric material layer is planarized to form a planarized first low-k dielectric material layer.
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公开(公告)号：US11856872B2
公开(公告)日：2023-12-26
申请号：US17204599
申请日：2021-03-17
发明人： Jaeho Jung , Kwangmin Park , Jonguk Kim , Dongsung Choi
CPC分类号： H10N70/066 , H10B63/845 , H10N70/063 , H10N70/068 , H10N70/841 , H10N70/883
摘要： A variable resistance memory device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction and crossing the first conductive lines in a plan view, and cell structures respectively provided at crossing points of the first conductive lines and the second conductive lines in the plan view. Each of the cell structures includes a switching pattern, a variable resistance pattern, and a first electrode provided between the switching pattern and the first conductive line, the first electrode including carbon. Each of the first conductive lines includes an upper pattern including a metal nitride in an upper portion thereof. The upper pattern is in contact with a bottom surface of the first electrode.
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8.发明授权公开(公告)号：US11476419B2
公开(公告)日：2022-10-18
申请号：US16874781
申请日：2020-05-15
发明人： Youngmin Ko , Jonguk Kim , Jaeho Jung , Dongsung Choi
摘要： A method for manufacturing a semiconductor device includes forming a first pattern structure having a first opening on a lower structure comprising a semiconductor substrate. The first pattern structure includes a stacked pattern and a first spacer layer covering at least a side surface of the stacked pattern. A first flowable material layer including a SiOCH material is formed on the first spacer layer to fill the first opening and cover an upper portion of the first pattern structure. A first curing process including supplying a gaseous ammonia catalyst into the first flowable material layer is performed on the first flowable material layer to form a first cured material layer that includes water. A second curing process is performed on the first cured material layer to form a first low-k dielectric material layer. The first low-k dielectric material layer is planarized to form a planarized first low-k dielectric material layer.
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公开(公告)号：US11411179B2
公开(公告)日：2022-08-09
申请号：US16933123
申请日：2020-07-20
发明人： Jaeho Jung , Kwangmin Park , Jonguk Kim , Dongsung Choi
摘要： A method of fabricating a variable resistance memory device that includes forming a plurality of memory cells on a substrate. Each of the plurality of memory cells in a switching device and a variable resistance pattern. A capping structure is formed that commonly covers lateral side surfaces of the plurality of memory cells. An insulating gapfill layer is formed that covers the capping structure and fills a region between adjacent memory cells of the plurality of memory cells. The forming of the capping structure includes forming a second capping layer including silicon oxide that covers the lateral side surfaces of the plurality of memory cells. At least a partial portion of the second capping layer is nitrided by performing a first decoupled plasma process to form a third capping layer that includes silicon oxynitride.
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公开(公告)号：US11930646B2
公开(公告)日：2024-03-12
申请号：US17224303
申请日：2021-04-07
发明人： Jeonghee Park , Jonguk Kim , Byeongju Bae
CPC分类号： H10B63/80 , H10B63/24 , H10N70/063 , H10N70/231
摘要： A resistive memory device includes a plurality of first conductive lines in a first area and a second area on a substrate, a plurality of second conductive lines in the first area and the second area, the plurality of second conductive lines being apart from the plurality of first conductive lines in a vertical direction, and a plurality of memory cells connected to the first and second conductive lines at a plurality of intersections between the plurality of first and second conductive lines in the first area and the second area. The plurality of memory cells include an active memory cell in the first area and a dummy memory cell in the second area. The active memory cell including a first resistive memory pattern having a first width and the dummy memory cell including a second resistive memory pattern having a second width greater than the first width.
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