-
公开(公告)号：US20240356562A1
公开(公告)日：2024-10-24
申请号：US18635948
申请日：2024-04-15
发明人： Win-San Khwa , Hiroki Noguchi , Ku-Feng Lin
CPC分类号： H03M7/16 , G11C11/1673 , H03K19/20
摘要： An encoding system may be provided. The encoding system may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.
-
公开(公告)号：US12009051B2
公开(公告)日：2024-06-11
申请号：US17747318
申请日：2022-05-18
发明人： Win-San Khwa , Jui-Jen Wu , Jen-Chieh Liu , Meng-Fan Chang
CPC分类号： G11C7/1096 , G11C7/06 , G11C7/1069
摘要： A method of storing an input data of a data set into a memory storage having bit cells. The method includes determining a bit value of a characterization bit in the input data. The method also includes writing each of remaining bits in the input data into one of the bit cells as a first state if the characterization bit has a first value, and writing each of remaining bits in the input data into the bit cells as a second state if the characterization bit has a second value that is complement to the first value. In the method, either reading the bit cell with the first state consumes less energy than reading the bit cell with the second state or the bit cell with the first state has less retention errors than the bit cell with the second state.
-
公开(公告)号：US11990194B2
公开(公告)日：2024-05-21
申请号：US17842790
申请日：2022-06-17
发明人： Win-San Khwa , Yi-Lun Lu , Jui-Jen Wu , Meng-Fan Chang
摘要： The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.
-
公开(公告)号：US20240152326A1
公开(公告)日：2024-05-09
申请号：US18163877
申请日：2023-02-03
发明人： Win-San Khwa , Meng-Fan Chang , Jui-Jen Wu , Chuan-Jia Jhang
CPC分类号： G06F7/5443 , G11C7/06 , G11C7/1096 , H04L9/0838
摘要： A memory device includes a memory array, a multiply-accumulate (MAC) circuit and an encoder-decoder circuit. The MAC circuit performs a MAC operation on an encoded weight data stored in the memory array and an input data to generate a partial MAC result. An encoder of the encoder-decoder circuit is configured to encode m weight bits among n weight bits of weight data according to an encryption key to generate the encoded weight data, wherein m and n are positive integers, and m is less than n. A decoder of the encoder-decoder circuit is configured to detect an error in the partial MAC result according to the encryption key to generate a decoded partial MAC result.
-
公开(公告)号：US11942185B2
公开(公告)日：2024-03-26
申请号：US17832261
申请日：2022-06-03
发明人： Je-Min Hung , Win-San Khwa , Meng-Fan Chang
CPC分类号： G11C7/222 , G06F7/5443 , G11C7/1063 , G11C7/109 , G11C7/12 , G11C7/14 , G11C7/16
摘要： An Input/Output (I/O) circuit for a memory device is provided. The I/O circuit includes a charge integration circuit coupled to a bitline of the memory device. The charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline. A comparator is coupled to the charge integration circuit. The comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison. A time-to-digital converter coupled to the comparator. The time-to-digital convertor converts a time associated with the output voltage to a digital value.
-
公开(公告)号：US20240079080A1
公开(公告)日：2024-03-07
申请号：US17901801
申请日：2022-09-01
发明人： Jui-Jen Wu , Jen-Chieh Liu , Yi-Lun Lu , Win-San Khwa , Meng-Fan Chang
CPC分类号： G11C29/46 , G11C29/1201 , G11C29/12015 , G11C2029/1202 , G11C2029/1204
摘要： A memory test circuit is provided. The memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.
-
公开(公告)号：US11664790B2
公开(公告)日：2023-05-30
申请号：US17736081
申请日：2022-05-03
发明人： Win-San Khwa , Jui-Jen Wu , Jen-Chieh Liu , Elia Ambrosi , Xinyu Bao , Meng-Fan Chang
摘要： A random number generator that includes control circuit, an oscillation circuit, an oscillation detection circuit and a latch circuit is introduced. The control circuit sweeps a configuration of a bias control signal among a plurality of configurations. The oscillation circuit generates an oscillation signal based on the configuration of the bias control signal. The oscillation detection circuit detects an onset of the oscillation signal, and outputs a lock signal. The latch circuit latches the oscillation signal according to a trigger signal to output a random number, wherein the trigger signal is asserted after the lock signal is outputted, and the configuration of bias control signal is locked after the lock signal is outputted. A method for generating a random number and an operation method of a random number generator are also introduced.
-
公开(公告)号：US20220359031A1
公开(公告)日：2022-11-10
申请号：US17408500
申请日：2021-08-23
发明人： Win-San Khwa , Jen-Chieh Liu , Meng-Fan Chang , Tung-Ying Lee , Jin Cai
摘要： A control circuit, a memory system and a control method are provided. The control circuit is configured to control a plurality of memory cells of a memory array. The control circuit comprises a program controller. The program is configured to program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type. A first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is smaller than a first predetermined value.
-
公开(公告)号：US20210174854A1
公开(公告)日：2021-06-10
申请号：US16709622
申请日：2019-12-10
发明人： Win-San Khwa , Hiroki Noguchi , Ku-Feng Lin
摘要： An encode apparatus and an encode method may be provided. The encoding apparatus may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.
-
公开(公告)号：US20240282349A1
公开(公告)日：2024-08-22
申请号：US18329557
申请日：2023-06-05
发明人： Tai-Hao Wen , Meng-Fan Chang , Win-San Khwa
CPC分类号： G11C7/1069 , G06F7/501 , G06F7/5443 , G11C7/1012 , G11C7/12
摘要： A memory system and operating method for controlling the same are provided. The memory system includes a memory array and a control circuit. The memory array comprising a first memory block and a second memory block, wherein the first memory block has a longer endurance than the second memory block. The control circuit is configured to receive a neural network model having a plurality of weight data; divide each of the plurality of weight data into a first data segment and a second data segment, wherein the first data segment has a higher bit order than the second data segment; and program the plurality of first data segments on the first memory block and program the plurality of second data segments on the second memory block.
-
-
-
-
-
-
-
-
-
搜索结果
43 条记录 (耗时 0.025 秒)
