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公开(公告)号：US11922240B2
公开(公告)日：2024-03-05
申请号：US17139226
申请日：2020-12-31
申请人： Ceremorphic, Inc.
发明人： Ryan Boesch , Martin Kraemer , Wei Xiong
摘要： A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.
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2.发明授权公开(公告)号：US12026479B2
公开(公告)日：2024-07-02
申请号：US17163494
申请日：2021-01-31
申请人： Ceremorphic, Inc.
发明人： Martin Kraemer , Ryan Boesch , Wei Xiong
摘要： A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to differential charge transfer lines through respective charge transfer capacitor Cu. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through a charge transfer capacitor Cu to charge transfer lines. Multiple Unit Elements may be placed in parallel to sum and scale the charges from the charge transfer lines, the charges coupled to an analog to digital converter which forms the dot product output.
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公开(公告)号：US12014151B2
公开(公告)日：2024-06-18
申请号：US17139935
申请日：2020-12-31
申请人： Ceremorphic, Inc.
发明人： Martin Kraemer , Ryan Boesch , Wei Xiong
CPC分类号： G06F7/5443 , H03M1/12
摘要： A plurality of unit elements share a charge transfer bus, each unit element accepts A and B digital inputs and generates a product P as an analog charge transferred to the charge transfer bus, each unit element comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates of each unit element are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges contributed by all unit elements to the charge transfer lines according to a bit weight and converted to a digital value output.
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公开(公告)号：US11983507B2
公开(公告)日：2024-05-14
申请号：US17139955
申请日：2020-12-31
申请人： Ceremorphic, Inc.
发明人： Martin Kraemer , Ryan Boesch , Wei Xiong
CPC分类号： G06F7/5443 , G06G7/16
摘要： A differential multiplier-accumulator accepts A and B digital inputs plus a sign bit and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. One of the positive and negative unit element is enabled by the sign bit, the enabled unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element, which charge to charge transfer lines, and the charge transfer lines are coupled to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product.
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公开(公告)号：US11632324B2
公开(公告)日：2023-04-18
申请号：US17334704
申请日：2021-05-29
申请人： Ceremorphic, Inc.
发明人： Robert Wiser , Venkat Mattela , Wei Xiong
IPC分类号： H04L45/02
摘要： A node mesh contains an originating node coupled to one or more nodes, each node having an communications interface input and a communications interface output. Each node has a route table with an association between a header amplitude and an output interface, such that a header having a particular amplitude causes the input node which received the message to couple the message to an associated communications interface output of the node. When the originating node outputs a message with a header amplitude, each node of the node mesh in turn directs the message to an output interface as directed by the node local route table to a terminating node of the node mesh, where the terminating node may be a training processor or inference processor for machine learning applications.
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公开(公告)号：US12118331B2
公开(公告)日：2024-10-15
申请号：US17163588
申请日：2021-02-01
申请人： Ceremorphic, Inc.
发明人： Martin Kraemer , Ryan Boesch , Wei Xiong
CPC分类号： G06F7/5443 , G06F17/16 , H03K19/20 , H03M1/38
摘要： A Bias Unit Element (UE) comprises NAND gates with complementary outputs, the complementary outputs coupled through a charge transfer capacitor to a differential charge transfer bus comprising positive charge transfer lines and negative charge transfer lines. Each line of the differential charge transfer bus has a particular binary weighted line weight, such as 1, 2, 4, 2, 4, 8, and 4, 8, 16. Digital bias inputs are provided to the Bias UE NAND gate inputs, with a clear bit to initialize charge, and a sign input for enabling one of a positive Bias UE or negative Bias UE. A low-to-high transition causes a transfer of charge to the binary weighted charge transfer bus, thereby adding or subtracting a bias value from the charge transfer bus.
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公开(公告)号：US11977936B2
公开(公告)日：2024-05-07
申请号：US17139945
申请日：2020-12-31
申请人： Ceremorphic, Inc.
发明人： Martin Kraemer , Ryan Boesch , Wei Xiong
CPC分类号： G06G7/16 , G06F7/5443
摘要： A differential multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each positive and negative unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product. The charge transfer lines may span multiple unit elements.
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8.发明授权公开(公告)号：US11689213B2
公开(公告)日：2023-06-27
申请号：US17334782
申请日：2021-05-30
申请人： Ceremorphic, Inc.
发明人： Martin Kraemer , Ryan Boesch , Wei Xiong
摘要： An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.
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