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公开(公告)号：US10282170B2
公开(公告)日：2019-05-07
申请号：US15659393
申请日：2017-07-25
申请人： Intel Corporation
发明人： Mohammad Abdallah
摘要： A method for fast parallel adder processing. The method includes receiving parallel inputs from a communications path, wherein each input comprises one bit, adding the inputs using a parallel structure, wherein the parallel structure is optimized to accelerate the addition by utilizing a characteristic that the inputs are one bit each, and transmitting the resulting outputs to a subsequent stage.
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公开(公告)号：US10275219B2
公开(公告)日：2019-04-30
申请号：US15807147
申请日：2017-11-08
摘要： A Field-Programmable Gate Array (FPGA) implementation of a multiplier topology can provide a considerable increase in computation performance and cost benefit as compared to other approaches, particularly for large bit widths (e.g., for multiplication of large-bit numbers). A lack of sufficient input/output (I/O) ports on the FPGA for a particular bit width can be remedied by implementing large-bit number multiplications in a bit-serial fashion. The bit-serial multiplier topologies described herein can provide a relatively small footprint as compared to other approaches. An FPGA-implemented bit-serial multiplier can improve operation of a computing system, for example, by offloading binary multiplication operations from a general-purpose processor.
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公开(公告)号：US20190056959A1
公开(公告)日：2019-02-21
申请号：US16078473
申请日：2016-08-22
IPC分类号： G06F9/4401 , G06F13/12 , G06F13/10 , G06F7/504
摘要： An example system includes a processor. The system also includes a peripheral interface that includes a controller communicatively coupled to the processor. The controller is to request information from a plurality of devices connected to the peripheral interface prior to the processor requesting the information. The controller is to provide the information to the processor.
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公开(公告)号：US20170228215A1
公开(公告)日：2017-08-10
申请号：US15017330
申请日：2016-02-05
申请人： SONY CORPORATION
CPC分类号： G06F7/523 , G06F7/5045 , G06F7/509
摘要： Various aspects of a system and method to process data in an adder based circuit, such as an integrated circuit, are disclosed herein. In accordance with an embodiment, a first addend is encoded as a first unary number. The first unary number comprises a token bit. A second addend is encoded as a second unary number. A first shift operation is performed on the token bit in the first unary number based on the second unary number. The first shift operation is performed to generate an output unary number. The generated output unary number is decoded to a number representation that corresponds to the number representation of the first addend and/or the second addend. The decoded number representation indicates a summation of the first addend and the second addend.
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公开(公告)号：US5189635A
公开(公告)日：1993-02-23
申请号：US828386
申请日：1992-01-30
申请人： Mitsuharu Ohki
发明人： Mitsuharu Ohki
CPC分类号： G06F7/504 , G06F2207/3884
摘要： A digital data processing circuit includes an adder circuit supplied with input data in a time-division multiplexed manner over a plurality of signal lines. The adder circuit is capable of executing additions at an optimum processing speed depending on the rate of the input data, and has a reduced circuit scale. The digital data processing circuit includes a 2-input data selector, a first register, a first full adder for supplying a carry output through the first register to one input terminal of the 2-input data selector, a second register, and a second full adder for supplying a carry output through the second register to the other input terminal of the 2-input data selector. The first and second full adders have input terminals for receiving first and second data supplied in a time-division multiplexed manner. The 2-input data selector is controlled to select the supplied carry outputs for producing the sum of the first and second data as sum outputs from the first and second full adders.
摘要翻译： 数字数据处理电路包括在多条信号线上以时分复用方式提供输入数据的加法器电路。 加法器电路能够根据输入数据的速率以最佳处理速度执行加法，并且具有减小的电路规模。 数字数据处理电路包括2输入数据选择器，第一寄存器，第一全加器，用于通过第一寄存器将进位输出提供给2输入数据选择器的一个输入端，第二寄存器和第二满 加法器，用于将通过第二寄存器的进位输出提供给2输入数据选择器的另一个输入端。 第一和第二全加器具有用于接收以时分复用方式提供的第一和第二数据的输入端。 控制2输入数据选择器以选择提供的进位输出，以产生第一和第二数据的和作为来自第一和第二全加器的和输出。
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公开(公告)号：US4920509A
公开(公告)日：1990-04-24
申请号：US167787
申请日：1988-03-11
申请人： Hedi Hmida , Pierre Duhamel
发明人： Hedi Hmida , Pierre Duhamel
摘要： A circuit for performing binary calculation, the circuit being of the type having at least one cell possessing: a first bit input (Ai), a second bit input (Bi), a carry-in input (Ri-1), circuitry (1600) for generating a two input bit exclusive-OR signal (Ai.sym.Bi) and its complement (Ai.sym.Bi), circuitry (1800) for producing a result signal, and circuitry (1900) for producing a carry-out signal (Ri), the circuitry being constituted by multiplexed logic. The complemented two input bit exclusive-OR signal (Ai.sym.Bi) is produced by inverting the two input bit exclusive-OR signal (Ai.sym.Bi), thereby making it possible to utilize only 15 transistors in the most cut-down version of the circuit. The invention also relates to a circuit (20) having an addition cell (22) calculating the sum of the input bits and a subtraction cell (24) calculating the difference of the input bits. The circuitry (1600) for producing the two input bit exclusive-OR signal (Ai.sym.Bi) and its complement (Ai.sym.Bi) are then used in common both by the addition cell (22) and by the subtraction cell (24).
摘要翻译： 一种用于执行二进制计算的电路，该电路具有至少一个具有第一位输入（Ai），第二位输入（Bi），进位输入（Ri-1），电路（1600） ）用于产生两个输入位异或信号（Ai（+）Bi）及其补码（Ai（+）Bi），用于产生结果信号的电路（1800），以及用于产生进位输出 信号（Ri），电路由多路复用逻辑构成。 通过将两个输入比特异或信号（Ai（+）Bi）反相来产生补码的两个输入比特异或信号（Ai（+）Bi），从而使得只能使用最多切入点的15个晶体管， 电路的下降版本。 本发明还涉及具有计算输入比特之和的加法单元（22）和计算输入比特差的减法单元（24）的电路（20）。 用于产生两个输入比特异或信号（Ai（+）Bi）及其补码（Ai（+）Bi）的电路（1600）然后由加法单元（22）和减法单元 （24）。
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公开(公告)号：US3769499A
公开(公告)日：1973-10-30
申请号：US3769499D
申请日：1972-04-04
发明人： HEIGHTLEY J
CPC分类号： G06F7/5045 , G06F2207/4818
摘要： The invention is a threshold logic three-input adder circuit comprising a combination of storage-processor elements. These elements are each arranged to decide which one of a pair of double-rail input signals has a higher potential and to store the result of that decision. Information stored in each element directs a unit of current through one or the other of two busses for summation and determination of the potentials of the busses. Current steering circuits responsive to the potential on a first one of the busses steer four, two, or no units of current through a second one of the busses. Carry and sum elements compare the potentials of the first and second busses with predetermined reference potentials to determine whether to store ''''ls'''' or ''''Os'''' resulting from the summation of the input signals.
摘要翻译： 本发明是包括存储处理器元件的组合的阈值逻辑三输入加法器电路。 这些元件每个被布置为确定一对双轨输入信号中的哪一个具有较高的电位并存储该决定的结果。 存储在每个元件中的信息通过两个总线中的一个或另一个引导电流单元来求和和确定总线的电位。 响应于第一个总线上的电位的当前转向回路引导四个，两个或不存在通过第二个总线的电流单元。 进位和和元素将第一和第二总线的电位与预定的参考电位进行比较，以确定是否存储由输入信号的和产生的“ls”或“Os”。
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公开(公告)号：US3594618A
公开(公告)日：1971-07-20
申请号：US3594618D
申请日：1968-06-21
申请人： NAT RES DEV
摘要： A logic element is described utilizing a travelling field domain phenomenon, such as the Gunn effect, which occurs in a body of material when a field is produced in the body above a first threshold value to nucleate a domain and is maintained above a second threshold value to sustain the domain. A plurality of contact means are carried on the body together with output means for detecting a field domain in the body and for deriving an output signal therefrom, and the arrangement is such that application between a predetermined number of the contact means of a potential just sufficient to create a field domain in the body produces an output signal at the output means, but the application of the same potential between a number of the contact means greater than the said predetermined number does not produce an output signal at the output means. One arrangement of the invention provides a comparator logic element having one primary electrode, and two secondary input electrodes, and a number of circuits utilizing this comparator are described.
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公开(公告)号：US3571615A
公开(公告)日：1971-03-23
申请号：US3571615D
申请日：1969-06-19
发明人： KELLY JAMES L
IPC分类号： G06F7/50 , G06F7/504 , G06F7/575 , H03K19/0185 , H03K19/173 , H03K19/08
CPC分类号： G06F7/504 , G06F7/575 , H03K19/018557 , H03K19/1733
摘要： A logic circuit module includes a pair of input coincidence gates whose outputs are applied to a carry flip-flop. The outputs of the input coincidence gates are buffered together and applied to separate output coincidence gates together with the outputs of the carry flip-flop. The logic module performs serial binary addition by employing each pair of input bits for gating out as their sum either the bit in the carry flip-flop or its complement. Moreover, by supplying appropriate control inputs to the input gates and the carry flip-flop, the module is capable of executing a plurality of logic functions.
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公开(公告)号：US3454751A
公开(公告)日：1969-07-08
申请号：US3454751D
申请日：1966-01-20
发明人： BRASTINS AUSEKLIS , WILLARD FRANK G
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