A digital data processing circuit includes an adder circuit supplied with input data in a time-division multiplexed manner over a plurality of signal lines. The adder circuit is capable of executing additions at an optimum processing speed depending on the rate of the input data, and has a reduced circuit scale. The digital data processing circuit includes a 2-input data selector, a first register, a first full adder for supplying a carry output through the first register to one input terminal of the 2-input data selector, a second register, and a second full adder for supplying a carry output through the second register to the other input terminal of the 2-input data selector. The first and second full adders have input terminals for receiving first and second data supplied in a time-division multiplexed manner. The 2-input data selector is controlled to select the supplied carry outputs for producing the sum of the first and second data as sum outputs from the first and second full adders.