公开(公告)号：US08149143B2

公开(公告)日：2012-04-03

申请号：US13083763

申请日：2011-04-11

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H03M7/00

CPC classification number: G06F7/503

Abstract: Methods and apparatus for implementing an n-state ripple-adder scheme coder with n≧2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems.

Abstract translation: 使用n状态可逆切换功能实现n≥2的n状态波纹加法器方案编码器的方法和装置，以及作用于至少2n的第一和第二字的不可逆n状态切换功能， 状态符号被公开。 还公开了相应的解码方法和装置。 所产生的码字可以是可以通过在对应的纹波加法器解码器中使用相同或不同的n状态切换功能来解码的码字。 Feistel网络和LFSR应用编码和解码。 使用编码和解码方法的系统可以是通信，存储和/或金融系统。

公开(公告)号：US20110182423A1

公开(公告)日：2011-07-28

申请号：US13083763

申请日：2011-04-11

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H04L9/30

CPC classification number: G06F7/503

Abstract: Methods and apparatus for implementing an n-state ripple-adder scheme coder with n≧2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems.

Abstract translation: 使用n状态可逆切换功能实现n≥2的n状态波纹加法器方案编码器的方法和装置，以及作用于至少2n的第一和第二字的不可逆n状态切换功能， 状态符号被公开。 还公开了相应的解码方法和装置。 所产生的码字可以是可以通过在对应的纹波加法器解码器中使用相同或不同的n状态切换功能来解码的码字。 Feistel网络和LFSR应用编码和解码。 使用编码和解码方法的系统可以是通信，存储和/或金融系统。

公开(公告)号：US07924176B2

公开(公告)日：2011-04-12

申请号：US12827465

申请日：2010-06-30

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H03M7/00

CPC classification number: G06F7/503

Abstract: Methods and apparatus for implementing an n-state ripple-adder scheme coder with n≧2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems.

Abstract translation: 使用n状态可逆切换功能实现n≥2的n状态波纹加法器方案编码器的方法和装置，以及作用于至少2n的第一和第二字的不可逆n状态切换功能， 状态符号被公开。 还公开了相应的解码方法和装置。 所产生的码字可以是可以通过在对应的纹波加法器解码器中使用相同或不同的n状态切换功能来解码的码字。 Feistel网络和LFSR应用编码和解码。 使用编码和解码方法的系统可以是通信，存储和/或金融系统。

公开(公告)号：US07716270B2

公开(公告)日：2010-05-11

申请号：US11374396

申请日：2006-03-13

Applicant: Joel Hatsch ,  Winfried Kamp

Inventor： Joel Hatsch ,  Winfried Kamp

IPC: G06F7/50

CPC classification number: G06F7/503

Abstract: A carry-ripple adder has four summing inputs for receiving four input bits having the significance w that are to be summed, three carry inputs for receiving three input carry bits having the significance w, a summation output for outputting an output summation bit having the significance w, and three carry outputs for outputting three output carry bits having the significance 2w.

Abstract translation: 进位纹波加法器具有四个加法输入，用于接收具有要求和的有效值w的四个输入位，三个进位输入用于接收具有有效值w的三个输入进位位;一个求和输出，用于输出具有重要性的输出求和位 w和三个进位输出，用于输出具有重要性2w的三个输出进位。

公开(公告)号：US07386583B2

公开(公告)日：2008-06-10

申请号：US10201265

申请日：2002-07-24

Applicant: Ki-seon Cho

Inventor： Ki-seon Cho

IPC: G06F7/50

CPC classification number: G06F7/507 ,  G06F7/503 ,  G06F2207/4812

Abstract: A conditional select adder having a carry generating unit which generates a carry of two n-bit input data units X0-Xn-1, and Y0-Yn-1, and a sum generating unit which generates the sum of the input data, is provided. The carry generating unit comprises a first input unit which receives predetermined data based on the input data Xi and Yi; a second input unit which receives the initial carry; and a selection unit which receives the result of performing an XOR operation on the input data Xi and Yi, in which according to the XOR result, either predetermined data based on the input data Xi and Yi input to the first input unit, or the initial carry input to the second input unit is selected and output as a carry. The sum generating unit calculates a sum using the carry generated by the carry generating unit. Advantages include reducing power consumption, chip area, logic count, and delay time.

Abstract translation: 一种条件选择加法器，具有进位产生单元，该进位产生单元产生两个n位输入数据单元X N-N N-1 N的进位和Y 0 < 提供了生成输入数据之和的和产生单元。 进位产生单元包括：第一输入单元，其基于输入数据X 1和Y 2 i接收预定数据; 接收初始进位的第二输入单元; 以及选择单元，其接收对输入数据X 1和Y 2进行XOR运算的结果，其中根据XOR结果，基于 选择输入到第一输入单元的输入数据X 1和I 2输入到第二输入单元的初始进位输入作为进位输出。 和产生单元使用由进位发生单元产生的进位来计算和。 优点包括降低功耗，芯片面积，逻辑计数和延迟时间。

公开(公告)号：US20060164119A1

公开(公告)日：2006-07-27

申请号：US10545641

申请日：2004-02-12

Applicant: Katarzyna Nowak-Leijten

Inventor： Katarzyna Nowak-Leijten

IPC: H03K19/177

CPC classification number: H03K19/17728 ,  G06F7/503 ,  H03K19/1737

Abstract: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. The input circuit can be configured to supply logic input signals from the same combination of the logic inputs to the programmable logic units in the random logic mode. In the multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain. The output circuit selects an output signal from the programmable logic units under control of further input signals in the random logic mode and passes outputs from the programmable logic units in parallel in the multi-bit operand mode. The programmable logic units comprise a multiplexer for passing one of the received input signals when configured to operate in the multiplexing mode of operation. Control signals may be shared between the multiplexing mode and the multi-bit operand processing mode.

Abstract translation: 电子电路具有可编程逻辑单元，其具有多个可编程逻辑单元，其能够被配置为以多位操作数模式和随机逻辑模式操作。 可编程逻辑单元在输入电路和输出电路之间并联耦合。 输入电路可以被配置为以随机逻辑模式将来自逻辑输入的相同组合的逻辑输入信号提供给可编程逻辑单元。 在多位操作数处理模式中，输入电路被配置为将逻辑输入信号从不同的逻辑输入提供给可编程逻辑单元。 可编程逻辑单元至少在多位操作数模式下沿着进位链耦合到连续位置，以便处理来自进位链的进位信号。 输出电路在随机逻辑模式下的其他输入信号的控制下从可编程逻辑单元中选择输出信号，并以多位操作数模式并行传送可编程逻辑单元的输出。 可编程逻辑单元包括多路复用器，用于当被配置为在多路复用操作模式下操作时，使所接收的输入信号之一通过。 控制信号可以在多路复用模式和多位操作数处理模式之间共享。

公开(公告)号：US20060158218A1

公开(公告)日：2006-07-20

申请号：US10545643

申请日：2004-02-12

Applicant: Katarzyna Leijten-Nowak

Inventor： Katarzyna Leijten-Nowak

IPC: H03K19/177

CPC classification number: G06F7/503 ,  G06F7/5272 ,  G11C16/10 ,  H03K19/1737 ,  H03K19/17728

Abstract: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a multiplexing mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. In a multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain. An output circuit passes outputs from the programmable logic units in parallel in the multi-bit operand mode. The programmable logic units have look-up tables which share the same configuration bits. The programmable logic units can also have multiplexers for passing one of the received input signals when configured to operate in a multiplexing mode of operation.

Abstract translation: 电子电路具有可编程逻辑单元，其具有多个可编程逻辑单元，其能够被配置为以多位操作数模式和复用模式操作。 可编程逻辑单元在输入电路和输出电路之间并联耦合。 在多位操作数处理模式中，输入电路被配置为将逻辑输入信号从不同的逻辑输入提供给可编程逻辑单元。 可编程逻辑单元至少在多位操作数模式下沿着进位链耦合到连续位置，以便处理来自进位链的进位信号。 输出电路在多位操作数模式下并行传送可编程逻辑单元的输出。 可编程逻辑单元具有共享相同配置位的查找表。 可编程逻辑单元还可以具有多路复用器，用于当被配置为在多路复用操作模式下操作时，使所接收的输入信号之一通过。

公开(公告)号：US20040167957A1

公开(公告)日：2004-08-26

申请号：US10781824

申请日：2004-02-20

Inventor： Chang-Jun Choi

IPC: G06F007/50

CPC classification number: G06F7/507 ,  G06F7/503 ,  G06F7/508

Abstract: A carry look-ahead adder may include: a carry generation circuit to generate carry propagation bit values and carry kill bit values for M blocks based on an N-bit addend and augend; a block carry circuit to generate block carry signals based upon the bit values; a Manchester-carry-chain configured bit carry circuit to generate first bit carry signals where a block carry exists in each of the M blocks and second carry bit signals where no block carry exists, based on the bit values; a control circuit to generate, independently of a clock enable signal at a logical level, selection-control signals based upon the block carry signals; and a summation selection circuit to select between the first bit carry signals and the second bit carry signals and to add the carry propagation bit values and the selected carry signals.

Abstract translation: 进位预读加法器可以包括：进位产生电路，用于基于N位加数和加法来产生进位传播比特值并携带M个块的禁止比特值; 块携带电路，用于基于比特值产生块进位信号; 一个曼彻斯特携带链配置的比特进位电路，用于产生第一比特进位信号，其中存在于每个M个块中的块进位和不存在任何块携带的第二进位比特信号; 控制电路，用于独立于逻辑电平的时钟使能信号，基于所述块进位信号产生选择控制信号; 以及求和选择电路，用于在第一比特进位信号和第二比特进位信号之间进行选择，并加上进位传播比特值和所选择的进位信号。

公开(公告)号：US06367059B1

公开(公告)日：2002-04-02

申请号：US09273580

申请日：1999-03-23

Applicant: Scott T. Becker

Inventor： Scott T. Becker

IPC: G06F1750

CPC classification number: G06F7/503

Abstract: A standard cell circuit architecture and design is provided by way of this disclosure. The standard cell has a plurality of sub-cells that are designed to function together to generate a result and the plurality of sub-cells have at least one input. The standard cell further includes a protection device connected just before and to the at least one input of the plurality of sub-cells. The protection device is designed to prevent charge sharing with circuitry of another standard cell that may be electrically coupled to the standard cell by way of the at least one input. In a specific application of the standard cell, the standard cell can be designed to be a carry chain standard cell. The carry chain standard cell can then be incorporated as part of a library of cells that may be used by a software synthesis layout tool.

Abstract translation: 通过本公开提供了标准单元电路架构和设计。 标准单元具有被设计为一起工作以产生结果并且多个子单元具有至少一个输入的多个子单元。 标准单元进一步包括紧接在多个子单元的至少一个输入端之间连接的保护装置。 保护装置被设计成防止与可以通过至少一个输入电耦合到标准单元的另一标准单元的电路的电荷共享。 在标准细胞的具体应用中，标准细胞可被设计为携带链标准细胞。 携带链标准单元可以作为可由软件合成布局工具使用的单元库的一部分而被并入。

公开(公告)号：US06288570B1

公开(公告)日：2001-09-11

申请号：US09679151

申请日：2000-10-03

Applicant: Bernard J. New

Inventor： Bernard J. New

IPC: H03K19177

CPC classification number: G06F7/503 ,  G06F7/507 ,  G06F2207/4812 ,  H03K19/1737

Abstract: Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal. For each bit, a carry propagate signal is generated by a lookup table programmable function generator and is used by dedicated hardware to generate the carry signal.

Abstract translation: 使用包括组合函数发生器和存储元件的多个块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。 当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。 本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。 本发明利用以下事实：当要添加的两个二进制比特不相等时，要添加到两个比特的进位信号可以被传播到下一个更高有效比特，并且该比特中的一个可以用作进位信号，当 这些位是相等的。 对于每个位，进位传播信号由查找表可编程函数发生器产生，并被专用硬件用于生成进位信号。