公开(公告)号：US07487198B2

公开(公告)日：2009-02-03

申请号：US10961521

申请日：2004-10-08

申请人： Joel Hatsch ,  Winfried Kamp

发明人： Joel Hatsch ,  Winfried Kamp

IPC分类号： G06F7/50

CPC分类号： G06F7/607 ,  H03K19/215 ,  H03K19/23

摘要： The invention relates to an adder for adding at least four bits of the same significance w, said adder having a first number of inputs for receiving the bits of the same significance w that are to be added and a number of outputs, the bits to be added being applied to the inputs in presorted form, and the adder adding the bits while taking account of the presorting. The invention also provides an adding device for adding at least four bits of equal significance and a corresponding method.

摘要翻译： 本发明涉及一种加法器，用于将相同含义w的至少四个比特相加，所述加法器具有第一数量的输入，用于接收与要相加的相同含义w的比特和多个输出， 以预分解形式将其应用于输入，加法器在考虑到预分频时加入位。 本发明还提供了一种用于添加至少四位具有相同重要性的添加装置和相应的方法。

公开(公告)号：US20060294178A1

公开(公告)日：2006-12-28

申请号：US11203445

申请日：2005-08-12

申请人： Marc Bernhardt ,  Joel Hatsch ,  Winfried Kamp ,  Siegmar Koeppe

发明人： Marc Bernhardt ,  Joel Hatsch ,  Winfried Kamp ,  Siegmar Koeppe

IPC分类号： G06F7/50

CPC分类号： G06F7/607 ,  G06F7/509 ,  G06F7/5318 ,  G06F2207/3872

摘要： A carry-ripple adder having inputs for supplying three input bits of equal significance 2n that are to be summed and two carry bits of equal significance 2n+1 that are also to be summed. A calculated sum bit of significance 2n and two calculated carry bits of equal significance 2n+1 which are higher than the significance 2n of the sum bit are provided at outputs. A final carry-ripple stage VMA may be used even after a reduction to three bits.

摘要翻译： 具有输入的输入纹波加法器，其具有用于提供要求和的三个等号有效值的输入比特和两个相等重要性的两个进位比特2 n + 1，也是 被总结。 计算出的有效值的和位2＆lt; n＆gt;和两个具有相同重要性的计算的进位位2＆lt; n + 1＆lt; / 2＆gt;其高于 在输出端提供和位。 即使在减少到三位之后，也可以使用最终的进位纹波级VMA。

公开(公告)号：US20050094477A1

公开(公告)日：2005-05-05

申请号：US10943701

申请日：2004-09-17

申请人： Joel Hatsch ,  Winfried Kamp ,  Thomas Kunemund ,  Holger Sedlak ,  Heinz Soldner

发明人： Joel Hatsch ,  Winfried Kamp ,  Thomas Kunemund ,  Holger Sedlak ,  Heinz Soldner

IPC分类号： G11C15/04 ,  G11C8/02

CPC分类号： G11C15/04

摘要： One embodiment provides a content addressable memory cell having a first memory cell which is electrically connected to a comparator unit. The comparator unit is constructed from at least eight transistors, at least four transistors being arranged in a first circuit part and at least four transistors being arranged in a second circuit part and each of the circuit parts having at least two circuit branches.

公开(公告)号：US08854866B2

公开(公告)日：2014-10-07

申请号：US13163131

申请日：2011-06-17

申请人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe ,  Thomas Kuenemund

发明人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe ,  Thomas Kuenemund

IPC分类号： G11C11/00 ,  G06F21/72 ,  H04L9/08

CPC分类号： H04L9/0866 ,  G06F21/72

摘要： A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.

摘要翻译： 半导体器件包括识别电路。 识别电路包括存储单元，其包括具有第一开关特性值的第一晶体管和具有第二开关特性值的第二晶体管。 识别电路可操作以产生依赖于第一晶体管的第一开关特性和第二晶体管的第二开关特性中生产规定的差异的存储单元特定的识别位。 识别电路还包括用于存储单元的驱动电路。 驱动电路可操作以独立于彼此连接或隔离半导体器件的上电源电位和较低电源电压到存储器单元或从存储器单元隔离。

公开(公告)号：US20120020145A1

公开(公告)日：2012-01-26

申请号：US13163131

申请日：2011-06-17

申请人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe

发明人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe

IPC分类号： G11C11/40 ,  G11C8/08

CPC分类号： H04L9/0866 ,  G06F21/72

摘要： A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.

摘要翻译： 半导体器件包括识别电路。 识别电路包括存储单元，其包括具有第一开关特性值的第一晶体管和具有第二开关特性值的第二晶体管。 识别电路可操作以产生依赖于第一晶体管的第一开关特性和第二晶体管的第二开关特性中生产规定的差异的存储单元特定的识别位。 识别电路还包括用于存储单元的驱动电路。 驱动电路可操作以独立于彼此连接或隔离半导体器件的上电源电位和较低电源电压到存储器单元或从存储器单元隔离。

公开(公告)号：US20050114424A1

公开(公告)日：2005-05-26

申请号：US10961521

申请日：2004-10-08

申请人： Joel Hatsch ,  Winfried Kamp

发明人： Joel Hatsch ,  Winfried Kamp

IPC分类号： G06F7/50 ,  G06F7/60 ,  H03K19/21 ,  H03K19/23

CPC分类号： G06F7/607 ,  H03K19/215 ,  H03K19/23

摘要： The invention relates to an adder for adding at least four bits of the same significance w, said adder having a first number of inputs for receiving the bits of the same significance w that are to be added and a number of outputs, the bits to be added being applied to the inputs in presorted form, and the adder adding the bits while taking account of the presorting. The invention also provides an adding device for adding at least four bits of equal significance and a corresponding method.

摘要翻译： 本发明涉及一种加法器，用于将相同含义w的至少四个比特相加，所述加法器具有第一数量的输入，用于接收与要相加的相同含义w的比特和多个输出， 以预分解形式将其应用于输入，加法器在考虑到预分频时加入位。 本发明还提供了一种用于添加至少四位具有相同重要性的添加装置和相应的方法。

公开(公告)号：US20060235923A1

公开(公告)日：2006-10-19

申请号：US11374396

申请日：2006-03-13

申请人： Joel Hatsch ,  Winfried Kamp

发明人： Joel Hatsch ,  Winfried Kamp

IPC分类号： G06F7/50

CPC分类号： G06F7/503

摘要： A carry-ripple adder has four summing inputs for receiving four input bits having the significance w that are to be summed, three carry inputs for receiving three input carry bits having the significance w, a summation output for outputting an output summation bit having the significance w, and three carry outputs for outputting three output carry bits having the significance 2 w.

摘要翻译： 进位纹波加法器具有四个加法输入，用于接收具有要求和的有效值w的四个输入位，三个进位输入用于接收具有有效值w的三个输入进位位;一个求和输出，用于输出具有重要性的输出求和位 w和三个进位输出，用于输出具有重要性2 w的三个输出进位。

公开(公告)号：US06735742B2

公开(公告)日：2004-05-11

申请号：US09864979

申请日：2001-05-24

申请人： Joel Hatsch ,  Winfried Kamp ,  Ronald Künemund ,  Eva Lackerschmid ,  Heinz Söldner

发明人： Joel Hatsch ,  Winfried Kamp ,  Ronald Künemund ,  Eva Lackerschmid ,  Heinz Söldner

IPC分类号： G06F1750

CPC分类号： G06F17/5045 ,  G06F17/5068 ,  H01L27/0207 ,  H01L27/118

摘要： A method for optimizing the layout of cells of an integrated circuit includes providing a cell-based network list with references to cell definitions with parameterizable dimensions, calculating a layout of an integrated circuit using the cell-based network list, extracting a primary network list from the layout, optimizing the component dimensions of at least some of the components of the integrated circuit using at least one predetermined optimization parameter and a simulation using the primary network list, creating an optimized secondary network list using the results of the component optimization, and automatically modifying the layout with respect to cell dimensions using a secondary network list.

摘要翻译： 一种用于优化集成电路的单元布局的方法包括：提供具有可参数化维度的单元定义的参考的基于单元的网络列表，使用基于单元的网络列表计算集成电路的布局，从 布局，使用至少一个预定的优化参数和使用主网络列表的模拟来优化集成电路的至少一些组件的组件尺寸，使用组件优化的结果创建优化的辅助网络列表，并且自动地 使用辅助网络列表修改关于单元格尺寸的布局。

公开(公告)号：US08605526B2

公开(公告)日：2013-12-10

申请号：US13118687

申请日：2011-05-31

申请人： Peter Huber ,  Joel Hatsch ,  Karl Hofmann ,  Siegmar Koeppe

发明人： Peter Huber ,  Joel Hatsch ,  Karl Hofmann ,  Siegmar Koeppe

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C29/12 ,  G11C29/50 ,  G11C2029/1204

摘要： Rather than merely carrying out a BIST test by verifying whether a memory cell accurately stores a “1” or “0” under normal read/write conditions, aspects of the present discloser relate to BIST tests that test the read and/or write margins of a cell. During this BIST testing, the read and/or write margins can be incrementally stressed until a failure point is determined for the cell. In this way, “weak” memory cells in an array can be identified and appropriate action can be taken, if necessary, to deal with these weak cells.

摘要翻译： 而不是仅仅通过验证存储器单元在正常读/写条件下是否准确地存储“1”或“0”来进行BIST测试，而本发明的方面涉及测试读取和/或写入边缘的BIST测试 一个单元格 在此BIST测试期间，读取和/或写入边距可以递增应力，直到为单元格确定故障点。 以这种方式，可以识别阵列中的“弱”存储单元，并且如果需要可以采取适当的动作来处理这些弱电池。

公开(公告)号：US20120307579A1

公开(公告)日：2012-12-06

申请号：US13118687

申请日：2011-05-31

申请人： Peter Huber ,  Joel Hatsch ,  Karl Hofmann ,  Siegmar Koeppe

发明人： Peter Huber ,  Joel Hatsch ,  Karl Hofmann ,  Siegmar Koeppe

IPC分类号： G11C29/12

CPC分类号： G11C29/12 ,  G11C29/50 ,  G11C2029/1204

摘要： Some embodiments of the present disclosure relate to improved reliability verification techniques for semiconductor memories. Rather than merely carrying out a BIST test by verifying whether a memory cell accurately stores a “1” or “0” under normal read/write conditions, aspects of the present invention relate to BIST tests that test the read and/or write margins of a cell. During this BIST testing, the read and/or write margins can be incrementally stressed until a failure point is determined for the cell. In this way, “weak” memory cells in an array can be identified and appropriate action can be taken, if necessary, to deal with these weak cells.

摘要翻译： 本公开的一些实施例涉及用于半导体存储器的改进的可靠性验证技术。 不是通过验证存储器单元在正常读/写条件下是否准确地存储1或0来执行BIST测试，而是本发明的方面涉及测试单元的读取和/或写入边缘的BIST测试。 在此BIST测试期间，读取和/或写入边距可以递增应力，直到为单元格确定故障点。 以这种方式，可以识别阵列中的弱记忆单元，并且如果需要，可以采取适当的动作来处理这些弱细胞。