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公开(公告)号：US10382014B2
公开(公告)日：2019-08-13
申请号：US15390397
申请日：2016-12-23
Applicant: ATI TECHNOLOGIES ULC , Advanced Micro Devices, Inc.
Inventor： Joyce Cheuk Wai Wong , Dragoljub Ignjatovic , Mikhail Rodionov , Ljubisa Bajic , Stephen V. Kosonocky , Steven J. Kommrusch
IPC: H03K3/03 , H03K3/012 , H03K3/013 , H03K3/0231 , H03K5/1534 , H03K5/15 , H03L5/00 , H03L7/099 , H03L1/02 , H03L7/085
Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
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公开(公告)号：US20190199363A1
公开(公告)日：2019-06-27
申请号：US15850593
申请日：2017-12-21
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stephen V. Kosonocky , Mikhail Rodionov , Joyce C. Wong
CPC classification number: H03L7/0992 , G06F1/08 , H03B1/04 , H03K3/0307 , H03K3/0372 , H03K2005/00071
Abstract: A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A master oscillator circuit receives a regulated supply voltage and supplies a master oscillator signal. A control circuit supplies a master frequency control signal to control a frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to a regulated supply voltage and a droopy supply voltage and supplies a slave oscillator signal having a frequency responsive to a slave frequency control signal that is based on the master frequency control signal. The frequency of the second oscillator signal is further responsive to a voltage change of the droopy supply voltage.
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公开(公告)号：US20180183413A1
公开(公告)日：2018-06-28
申请号：US15390397
申请日：2016-12-23
Applicant: ATI TECHNOLOGIES ULC , Advanced Micro Devices, Inc.
Inventor： Joyce Cheuk Wai Wong , Dragoljub Ignjatovic , Mikhail Rodionov , Ljubisa Bajic , Stephen V. Kosonocky , Steven J. Kommrusch
CPC classification number: H03K3/013 , H03K3/012 , H03K3/0231 , H03K3/03 , H03K5/1506 , H03K5/1508 , H03K5/1534 , H03L1/02 , H03L5/00 , H03L7/085 , H03L7/0997
Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
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公开(公告)号：US11962313B2
公开(公告)日：2024-04-16
申请号：US16370479
申请日：2019-03-29
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stephen Victor Kosonocky , Mikhail Rodionov , Joyce Cheuk Wai Wong
CPC classification number: H03L7/0991 , H03K5/14 , H03K2005/00058
Abstract: An oscillator circuit is provided that adapts to voltage supply variations. The circuit first and second delays lines connected inputs of an edge detector, one delay line supplied by a reference voltage and the other with a drooping supply voltage. The edge detector generates an output clock based on a relationship between the inputs. The output clock applied to the signal inputs of the first and second delay lines. The output clock has a voltage dependent frequency performance curve with a slope dependent at least on the second delay line delay and a delay of the edge detector. At least one of the first delay line, the second delay line, and the edge detector delay are adjusted to change the slope of the performance curve.
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公开(公告)号：US11936382B2
公开(公告)日：2024-03-19
申请号：US16454596
申请日：2019-06-27
Applicant: ATI TECHNOLOGIES ULC , ADVANCED MICRO DEVICES, INC.
Inventor： Joyce Cheuk Wai Wong , Dragoljub Ignjatovic , Mikhail Rodionov , Ljubisa Bajic , Stephen V. Kosonocky , Steven J. Kommrusch
IPC: H03L1/02 , H03K3/012 , H03K3/013 , H03K3/0231 , H03K3/03 , H03K5/15 , H03L5/00 , H03L7/085 , H03L7/099 , H03K5/1534
CPC classification number: H03K3/013 , H03K3/012 , H03K3/0231 , H03K3/03 , H03K5/1506 , H03K5/1508 , H03L1/02 , H03L5/00 , H03L7/085 , H03L7/0997 , H03K5/1534
Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
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Patent Agency Ranking
公开(公告)号：US20230195191A1
公开(公告)日：2023-06-22
申请号：US17559111
申请日：2021-12-22
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Kaushik Mazumdar , Miguel Rodriguez , Mikhail Rodionov , Stephen Victor Kosonocky
CPC classification number: G06F1/28 , H03K19/20 , H03K5/2472 , H03K3/037
Abstract: A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.
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公开(公告)号：US12055991B2
公开(公告)日：2024-08-06
申请号：US17559111
申请日：2021-12-22
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Kaushik Mazumdar , Miguel Rodriguez , Mikhail Rodionov , Stephen Victor Kosonocky
CPC classification number: G06F1/28 , H03K3/037 , H03K5/2472 , H03K19/20
Abstract: A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.
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公开(公告)号：US20240106438A1
公开(公告)日：2024-03-28
申请号：US18525071
申请日：2023-11-30
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Kaushik Mazumdar , Ashish Jain , Joyce Cheuk Wai Wong , Mikhail Rodionov
IPC: H03L7/08 , G01R19/165
CPC classification number: H03L7/08 , G01R19/16552
Abstract: An integrated circuit includes a power supply monitor, a clock generator, and a divider. The power supply monitor is operable to provide a trigger signal in response to a power supply voltage dropping below a threshold voltage. The clock generator is operable to provide a first clock signal having a frequency dependent on a value of a frequency control word, and to change the frequency of the first clock signal over time using a native slope in response to a change in the frequency control word. The divider is responsive to an assertion of the trigger signal to divide a frequency of the first clock signal by a divide value to provide a second clock signal.
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公开(公告)号：US12278638B2
公开(公告)日：2025-04-15
申请号：US18525071
申请日：2023-11-30
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Kaushik Mazumdar , Ashish Jain , Joyce Cheuk Wai Wong , Mikhail Rodionov
IPC: H03L7/08 , G01R19/165
Abstract: An integrated circuit includes a power supply monitor, a clock generator, and a divider. The power supply monitor is operable to provide a trigger signal in response to a power supply voltage dropping below a threshold voltage. The clock generator is operable to provide a first clock signal having a frequency dependent on a value of a frequency control word, and to change the frequency of the first clock signal over time using a native slope in response to a change in the frequency control word. The divider is responsive to an assertion of the trigger signal to divide a frequency of the first clock signal by a divide value to provide a second clock signal.
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公开(公告)号：US10425089B2
公开(公告)日：2019-09-24
申请号：US15850593
申请日：2017-12-21
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stephen V. Kosonocky , Mikhail Rodionov , Joyce C. Wong
Abstract: A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A master oscillator circuit receives a regulated supply voltage and supplies a master oscillator signal. A control circuit supplies a master frequency control signal to control a frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to a regulated supply voltage and a droopy supply voltage and supplies a slave oscillator signal having a frequency responsive to a slave frequency control signal that is based on the master frequency control signal. The frequency of the second oscillator signal is further responsive to a voltage change of the droopy supply voltage.
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