公开(公告)号：US20190115928A1

公开(公告)日：2019-04-18

申请号：US16136046

申请日：2018-09-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YASUO SATOH

IPC: H03L7/193 ,  H03K21/10 ,  H03K5/13 ,  H03L7/08

CPC classification number: H03L7/193 ,  H03K5/13 ,  H03K21/10 ,  H03L7/0805 ,  H03L7/0997

Abstract: Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second arid third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.

公开(公告)号：US20180309455A1

公开(公告)日：2018-10-25

申请号：US16017421

申请日：2018-06-25

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.

Inventor： Paul PENZES ,  Mark FULLERTON

IPC: H03L7/08 ,  H03L7/099 ,  H03L7/097 ,  G06F1/32 ,  G06F12/14 ,  G06F21/44 ,  H03K3/03 ,  H03K3/037 ,  H03K19/01 ,  H03K5/133 ,  H03K5/00 ,  G06F1/26

CPC classification number: H03L7/0802 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3228 ,  G06F12/14 ,  G06F21/44 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/037 ,  H03K3/0375 ,  H03K5/133 ,  H03K19/01 ,  H03K2005/00019 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/097 ,  H03L7/0997 ,  H01L2924/00

Abstract: Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.

公开(公告)号：US10084460B2

公开(公告)日：2018-09-25

申请号：US15820701

申请日：2017-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingdong Deng ,  Chung S. Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

IPC: H03L7/06 ,  H03L7/087 ,  H03L7/099 ,  G06F17/50

CPC classification number: H03L7/087 ,  G06F17/5045 ,  H03L7/0991 ,  H03L7/0995 ,  H03L7/0997 ,  H03L2207/06 ,  H03L2207/50 ,  H05K999/99

Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

公开(公告)号：US09819350B2

公开(公告)日：2017-11-14

申请号：US15248816

申请日：2016-08-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingdong Deng ,  Chung S. Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

IPC: H03L7/06 ,  H03L7/087 ,  H03L7/099 ,  G06F17/50

CPC classification number: H03L7/087 ,  G06F17/5045 ,  H03L7/0991 ,  H03L7/0995 ,  H03L7/0997 ,  H03L2207/06 ,  H03L2207/50

Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

公开(公告)号：US09667262B2

公开(公告)日：2017-05-30

申请号：US15189017

申请日：2016-06-22

Applicant: DENSO CORPORATION

Inventor： Shigenori Yamauchi ,  Nobuyuki Taguchi ,  Takamoto Watanabe

IPC: H03K3/03 ,  H03L7/099 ,  H03L7/091 ,  H03L7/197 ,  H03K23/50 ,  G06F1/12 ,  H03K23/42 ,  H03K5/135 ,  G04F10/00

CPC classification number: H03L7/0997 ,  G04F10/005 ,  G06F1/12 ,  H03K3/0315 ,  H03K5/135 ,  H03K23/425 ,  H03K23/502 ,  H03L7/091 ,  H03L7/1974

Abstract: A digital control oscillator circuit includes: a ring oscillator having delay elements delaying a pulse signal; a counter circuit counting the circulation number of the pulse signal; a rough period generation unit acquiring a period setting value as a magnification ratio for a reference clock, and counting the reference clock using an integer part of the ratio to generate a rough period timing; a fraction conversion unit converting a decimal point part of the ratio into the number of the elements passed by the pulse signal to generate a fraction; and an output processing unit selecting a timing when outputs of the ring oscillator and the counter circuit become values corresponding to the fraction as an output timing when a time corresponding to the fraction has passed after the rough period timing, and generating an output signal oscillating at a period represented by the period setting value according to the output timing.

公开(公告)号：US20170117907A1

公开(公告)日：2017-04-27

申请号：US14681455

申请日：2015-04-08

Applicant: Infineon Technologies AG

Inventor： Werner GROLLITSCH

IPC: H03L7/099 ,  H03L7/087 ,  H03L7/24 ,  H03K3/03

CPC classification number: H03L7/0995 ,  H03K3/0315 ,  H03K3/0322 ,  H03L1/00 ,  H03L7/0802 ,  H03L7/087 ,  H03L7/091 ,  H03L7/099 ,  H03L7/0997 ,  H03L7/18 ,  H03L7/1974 ,  H03L7/22 ,  H03L7/24

Abstract: Representative implementations of devices and techniques provide reduced jitter for a controlled oscillator. An edge of a reference signal is injected at various points within the oscillator, and is replaced for an edge of the generated oscillation signal at the injection point.

公开(公告)号：US20170003708A1

公开(公告)日：2017-01-05

申请号：US15268085

申请日：2016-09-16

Applicant: INSIDE SECURE

Inventor： Vincent MIGAIROU ,  Julien ROCHE

IPC: G06F1/12 ,  G06F13/42 ,  H03K3/03

CPC classification number: G06F1/12 ,  G06F1/08 ,  G06F13/4282 ,  G06F2213/0042 ,  H03K3/0315 ,  H03K5/135 ,  H03L7/085 ,  H03L7/0997 ,  H03L7/22 ,  H03L2207/50

Abstract: In a general aspect, a method for adjusting an oscillator clock frequency can include applying a first control value to a first oscillator, applying a second control value, different from the first control value, to a second oscillator, measuring a frequency of each of the first and second oscillators, determining, by interpolation, a corrected frequency measurement of the second oscillator depending on a frequency deviation measured between the first and second oscillators when subjected to a third control value, on the third control value, and on the control value applied to the second oscillator, determining by interpolation a new first control value depending on the measured frequency of the first oscillator, on the corrected frequency, on the first and second control values, and on a desired frequency, and applying the new first control value to the first oscillator.

Abstract translation: 一般来说，一种用于调整振荡器时钟频率的方法可以包括：向第一振荡器施加第一控制值，将不同于第一控制值的第二控制值应用于第二振荡器，测量第一振荡器的频率 第一和第二振荡器，通过内插确定第二振荡器的校正频率测量值，该校正频率测量值取决于在受到第三控制值时在第一和第二振荡器之间测量的频率偏差，关于第三控制值，以及应用的控制值 到第二振荡器，通过插值确定取决于第一振荡器的测量频率，校正频率，第一和第二控制值以及期望频率上的新的第一控制值，并将新的第一控制值应用于 第一个振荡器。

公开(公告)号：US20160365864A1

公开(公告)日：2016-12-15

申请号：US15248822

申请日：2016-08-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingdong DENG ,  Chung S. HO ,  David S. FLYE ,  Zhenrong JIN ,  Ramana M. MALLADI

IPC: H03L7/087 ,  G06F17/50 ,  H03L7/099

CPC classification number: H03L7/087 ,  G06F17/5045 ,  H03L7/0991 ,  H03L7/0995 ,  H03L7/0997 ,  H03L2207/06 ,  H03L2207/50

Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

公开(公告)号：US20160072514A1

公开(公告)日：2016-03-10

申请号：US14497890

申请日：2014-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TSUNG-HSIEN TSAI

IPC: H03L7/099 ,  H03L7/08

CPC classification number: H03L7/0995 ,  H03B27/00 ,  H03K3/011 ,  H03K5/133 ,  H03L1/00 ,  H03L7/0802 ,  H03L7/093 ,  H03L7/099 ,  H03L7/0994 ,  H03L7/0997 ,  H03L2207/50

Abstract: In some embodiments, a digitally controlled oscillator includes a first oscillator a second oscillator and a switch. The second oscillator is selectively enabled in response to a controlled signal. The switch is coupled between the first oscillator and the second oscillator and is selectively conducted in response to the controlled signal, so that an oscillator signal is provided by the first oscillator when the switch is not conducted, and provided by the first oscillator and the second oscillator when the switch is conducted.

Abstract translation: 在一些实施例中，数字控制振荡器包括第一振荡器，第二振荡器和开关。 响应于受控信号，第二振荡器被选择性地使能。 开关耦合在第一振荡器和第二振荡器之间并且响应于受控信号选择性地导通，使得当开关不导通时由第一振荡器提供振荡器信号，并且由第一振荡器和第二振荡器提供振荡器信号 当开关导通时振荡器。

公开(公告)号：US20140320217A1

公开(公告)日：2014-10-30

申请号：US13873714

申请日：2013-04-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David T. Hui ,  Xiaobin Yuan

IPC: H03L7/00

CPC classification number: H03L7/00 ,  H03K3/0315 ,  H03L7/0997

Abstract: A digitally-controlled oscillator includes a base frequency generator having an odd number of base inverters connected end-to-end to generate an output signal that oscillates at a predetermined frequency and a frequency-adjusting unit connected to the base frequency generator. The frequency-adjusting unit includes a first string of switchable inverters connected in series with each other, the switchable inverters having sizes that decrease from an input end of the first string to the output end of the first string.

Abstract translation: 数字控制振荡器包括基本频率发生器，其具有端到端连接的奇数个基本反相器，以产生以预定频率振荡的输出信号和连接到基频发生器的频率调节单元。 频率调节单元包括彼此串联连接的第一串可切换逆变器，可切换逆变器具有从第一串的输入端到第一串的输出端减小的尺寸。