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公开(公告)号：US10958276B2
公开(公告)日：2021-03-23
申请号：US16733669
申请日：2020-01-03
摘要： A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.
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公开(公告)号：US20150024570A1
公开(公告)日：2015-01-22
申请号：US14508011
申请日：2014-10-07
IPC分类号： H01L29/66 , H01L21/311 , H01L21/02 , H01L21/762
CPC分类号： H01L29/66272 , G06F17/5009 , G06F17/5036 , G06F17/5068 , G06F2217/12 , H01L21/02532 , H01L21/02595 , H01L21/31111 , H01L21/76224 , H01L21/76229 , H01L21/76232 , H01L21/8249 , H01L27/0207 , H01L29/7322 , Y02P90/265
摘要： Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.
摘要翻译： 双极晶体管结构，双极晶体管的设计和制造方法，设计具有双极晶体管的电路的方法。 设计双极晶体管的方法包括：选择双极晶体管的初始设计; 缩放双极晶体管的初始设计以产生双极晶体管的缩放设计; 基于缩放之后双极晶体管的发射极的尺寸来确定双极晶体管的缩放设计的应力补偿是否需要; 并且如果需要对双极型晶体管的缩放设计的应力补偿，则调整缩放设计的沟槽隔离布局级别相对于缩放设计的发射器布局级别的布局的布局，以产生压缩补偿的缩放设计 双极晶体管。
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公开(公告)号：US10063243B2
公开(公告)日：2018-08-28
申请号：US15668790
申请日：2017-08-04
发明人： Jingdong Deng , Chung S. Ho , David Flye , Zhenrong Jin , Ramana M. Malladi
CPC分类号： H03L7/087 , G06F17/5045 , H03L7/0991 , H03L7/0995 , H03L7/0997 , H03L2207/06 , H03L2207/50 , H05K999/99
摘要： A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.
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公开(公告)号：US09076810B2
公开(公告)日：2015-07-07
申请号：US14508011
申请日：2014-10-07
IPC分类号： H01L21/331 , H01L29/66 , G06F17/50 , H01L21/8249 , H01L29/732 , H01L21/762 , H01L21/02 , H01L21/311 , H01L27/02
CPC分类号： H01L29/66272 , G06F17/5009 , G06F17/5036 , G06F17/5068 , G06F2217/12 , H01L21/02532 , H01L21/02595 , H01L21/31111 , H01L21/76224 , H01L21/76229 , H01L21/76232 , H01L21/8249 , H01L27/0207 , H01L29/7322 , Y02P90/265
摘要： Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.
摘要翻译： 双极晶体管结构，双极晶体管的设计和制造方法，设计具有双极晶体管的电路的方法。 设计双极晶体管的方法包括：选择双极晶体管的初始设计; 缩放双极晶体管的初始设计以产生双极晶体管的缩放设计; 基于缩放之后双极晶体管的发射极的尺寸来确定双极晶体管的缩放设计的应力补偿是否需要; 并且如果需要对双极型晶体管的缩放设计的应力补偿，则调整缩放设计的沟槽隔离布局级别相对于缩放设计的发射器布局级别的布局的布局，以产生压缩补偿的缩放设计 双极晶体管。
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公开(公告)号：US08912854B2
公开(公告)日：2014-12-16
申请号：US13734364
申请日：2013-01-04
CPC分类号： H03B5/1265 , G06F17/5045 , H03B5/04 , H03B5/1206 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/1253 , H03B7/02 , H03B7/06 , H03B2200/004 , H03B2200/005 , H03B2201/0208 , H03B2202/042 , H03L1/00 , H03L7/04
摘要： Embodiments of the present invention provide a design structure and method for compensating for a change in frequency of oscillation (FOO) of an LC-tank VCO that includes a first node; second node; inductor; first capacitive network (FCN) that allows the design structure to obtain a target FOO; compensating capacitive (CCN) network that compensates for a change in the design structure's FOO; second capacitive network (SCN) that allows the design structure to obtain a desired FOO; a filter that supplies a voltage to the SCN and is coupled to the SCN; a transconductor that compensates for a change in the design structure's FOO; and a sub-circuit coupled to the SCN that generates and supplies voltage to the CCN sufficient to allow the CCN to compensate for a reduction in the design structure's FOO. The first and second nodes are coupled to the inductor, FCN, CCN, SCN, and sub-circuit.
摘要翻译： 本发明的实施例提供了一种用于补偿包括第一节点的LC槽VCO的振荡频率（FOO）变化的设计结构和方法; 第二节点 电感; 第一电容网络（FCN），允许设计结构获得目标FOO; 补偿电容（CCN）网络，补偿设计结构的FOO的变化; 第二电容网络（SCN），其允许设计结构获得期望的FOO; 一个向SCN提供电压并耦合到SCN的滤波器; 一种补偿设计结构FOO变化的跨导体; 以及耦合到SCN的子电路，其产生并向CCN提供足够的电压以允许CCN补偿设计结构的FOO的减少。 第一和第二节点耦合到电感器，FCN，CCN，SCN和子电路。
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公开(公告)号：US20130130462A1
公开(公告)日：2013-05-23
申请号：US13740673
申请日：2013-01-14
发明人： David L. Harame , Alvin J. Joseph , Qizhi Liu , Ramana M. Malladi
IPC分类号： H01L29/73
CPC分类号： H01L29/73 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： Embodiments of the present invention include a method for forming a tunable semiconductor device. In one embodiment, the method comprises: forming a semiconductor substrate; patterning a first mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector; removing the first mask; patterning a second mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector; removing the second mask; and forming a single continuous collector above the second discontinuous subcollector.
摘要翻译： 本发明的实施例包括形成可调谐半导体器件的方法。 在一个实施例中，该方法包括：形成半导体衬底; 在半导体衬底上图案化第一掩模; 不受第一掩模保护的半导体衬底的掺杂区域以形成第一不连续子集电极; 去除第一个面罩; 在半导体衬底上图案化第二掩模; 所述半导体衬底的掺杂区域不被所述第二掩模保护并且在所述第一不连续子集电极的顶部上以形成第二不连续子集电极; 去除第二个掩模; 以及在第二不连续子集电极上方形成单个连续集电器。
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公开(公告)号：US10566981B2
公开(公告)日：2020-02-18
申请号：US16152678
申请日：2018-10-05
摘要： A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.
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公开(公告)号：US09455728B2
公开(公告)日：2016-09-27
申请号：US14245374
申请日：2014-04-04
发明人： Jingdong Deng , Chung S. Ho , David Flye , Zhenrong Jin , Ramana M. Malladi
CPC分类号： H03L7/087 , G06F17/5045 , H03L7/0991 , H03L7/0995 , H03L7/0997 , H03L2207/06 , H03L2207/50
摘要： A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.
摘要翻译： 公开了一种锁相环电路。 锁相环电路包括环形振荡器。 锁相环电路还包括包括数字相位检测器的数字路径。 锁相环电路还包括包括线性相位检测器的模拟路径。 此外，锁相环电路包括将环形振荡器的输出连接到数字路径的输入和模拟路径的输入的反馈路径。 数字路径和模拟路径是并行路径。 数字通道提供数字调谐信号，环形振荡器数字控制环形振荡器的频率。 模拟通道提供模拟调谐信号，环形振荡器可以连续控制环形振荡器的频率。
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公开(公告)号：US09159801B2
公开(公告)日：2015-10-13
申请号：US14496242
申请日：2014-09-25
IPC分类号： H01L29/66 , H01L29/732 , H01L29/08 , G06F17/50 , H01L29/06 , H01L29/10 , H01L29/735
CPC分类号： H01L29/66303 , G06F17/5045 , H01L29/0649 , H01L29/0804 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/66234 , H01L29/7322 , H01L29/735
摘要： Bipolar junction transistors and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process.
摘要翻译： 双极结晶体管和双极结晶体管的设计结构。 双极结晶体管可以包括布置在不同的发射极指中的多个发射极。 形成了覆盖双极结型晶体管的非本征基极层并填充相邻发射极之间的间隙的硅化物层。 发射极侧壁上的非导电间隔物使发射体与硅化物层电绝缘。 发射极延伸通过外部基极层和硅化物层与本征基极层接触。 发射器可以在替代型工艺中使用牺牲发射器基座形成。
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公开(公告)号：US20150008559A1
公开(公告)日：2015-01-08
申请号：US14496242
申请日：2014-09-25
IPC分类号： H01L29/735 , H01L29/08 , H01L29/10 , G06F17/50 , H01L29/06
CPC分类号： H01L29/66303 , G06F17/5045 , H01L29/0649 , H01L29/0804 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/66234 , H01L29/7322 , H01L29/735
摘要： Bipolar junction transistors and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process.
摘要翻译： 双极结晶体管和双极结晶体管的设计结构。 双极结晶体管可以包括布置在不同的发射极指中的多个发射极。 形成了覆盖双极结型晶体管的非本征基极层并填充相邻发射极之间的间隙的硅化物层。 发射极侧壁上的非导电间隔物使发射体与硅化物层电绝缘。 发射极延伸通过外部基极层和硅化物层与本征基极层接触。 发射器可以在替代型工艺中使用牺牲发射器基座形成。
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