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公开(公告)号：US12081224B2
公开(公告)日：2024-09-03
申请号：US17807452
申请日：2022-06-17
CPC分类号： H03L7/24 , G06F1/14 , G06F9/4812 , H03L7/0992
摘要： In an embodiment a method includes generating a low-frequency clock signal having a first frequency, in a standby mode and in a run mode of the CPU, generating a high-frequency clock signal having a second frequency higher than the first frequency, in the run mode, updating a value of the reference time base at each period of the low-frequency clock signal in the standby mode, and accessing the counter register with the high-frequency clock signal in the run mode.
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公开(公告)号：US20240275393A1
公开(公告)日：2024-08-15
申请号：US18168544
申请日：2023-02-13
发明人： Jia-Ming HE , Yaw-Guang CHANG , Yu-Han CHEN
CPC分类号： H03L7/0992 , H03L7/101 , H03L7/24
摘要： The invention provides a power system for monitoring a working environment of a monitored circuit and adjusting a working voltage of the monitored circuit includes: a power circuit, a voltage-controlled oscillator and a counter. The power circuit is configured to output the working voltage to the monitored circuit through a power supply path. The voltage-controlled oscillator is disposed in or around the monitored circuit and is electrically connected to the power supply path and a ground path to which the monitored circuit is electrically connected, and is configured to output an oscillation frequency in accordance with a signal variation on the power supply path and the ground path. The counter is electrically connected to the voltage-controlled oscillator and is configured to generate a counting number signal in accordance with the oscillation frequency and a synchronizing signal, thereby adjusting the working voltage outputted to the monitored circuit.
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公开(公告)号：US20240171183A1
公开(公告)日：2024-05-23
申请号：US18430958
申请日：2024-02-02
发明人： Brent CARLSON
CPC分类号： H03L7/0991 , H03L7/141 , H03L7/24
摘要： A method for timing aperture synthesis arrays comprising the steps of: (a) coupling a plurality of independent crystal oscillators, each of the plurality of independent crystal oscillators having a unique output frequency; (b) digitally synchronizing the plurality of independent crystal oscillators in phase; (c) combining the unique output frequencies; and (d) obtaining a stable digital reference signal for timing at least one remote radio device of the aperture synthesis array.
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公开(公告)号：US11777509B2
公开(公告)日：2023-10-03
申请号：US17871433
申请日：2022-07-22
发明人： Yu-Jiu Wang , Bor-Ching Su
IPC分类号： H03L7/18 , H03K23/66 , H03L7/24 , H03L7/00 , H04L7/00 , H04W56/00 , H03K21/00 , G01S7/02 , G01S7/295 , G01S13/34 , H04B7/06
CPC分类号： H03L7/18 , H03K21/00 , H03K23/662 , H03K23/667 , H03L7/00 , H03L7/24 , H04L7/0008 , H04L7/0037 , H04W56/004 , G01S7/021 , G01S7/295 , G01S13/341 , H04B7/0617
摘要： A radar system includes: a plurality of first receiving devices for generating a plurality of first digital signals according to a plurality of first incoming signals, respectively; and a plurality of second receiving devices for generating a plurality of second digital signals according to a plurality of second incoming signals, respectively. A processing device is arranged to perform a first beamforming operation to generate a plurality of first beamforming signals according to the plurality of first digital signals and a first gain matrix, and to perform a second beamforming operation to generate a plurality of second beamforming signals according to the plurality of second digital signals and a second gain matrix; and to determine an altitude angle of a first object and a second object, and to determine a first azimuth angle of the first object and a second azimuth angle of the second object.
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公开(公告)号：US11750199B2
公开(公告)日：2023-09-05
申请号：US17824537
申请日：2022-05-25
申请人： SOCIONEXT INC.
CPC分类号： H03L7/0805 , H03B5/1215 , H03B5/1228 , H03B27/00 , H03L7/099 , H03L7/24 , H03B2200/0078
摘要： Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.
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公开(公告)号：US11374577B2
公开(公告)日：2022-06-28
申请号：US17100350
申请日：2020-11-20
申请人： SOCIONEXT INC.
摘要： Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.
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公开(公告)号：US20220149850A1
公开(公告)日：2022-05-12
申请号：US17091072
申请日：2020-11-06
申请人： u-blox AG
摘要： An electronic device includes: a first input node configured to receive a dock signal; a second input node configured to receive an activation signal or a deactivation signal; a filter circuit responsive to: (a) the activation signal to activate the filter circuit to block the dock signal; or (b) the deactivation signal to deactivate the filter circuit to pass the dock signal; and an output node configured for coupling to a synchronous I/O interface of an integrated circuit to control operation of the synchronous I/O interface.
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公开(公告)号：US11303289B2
公开(公告)日：2022-04-12
申请号：US17002967
申请日：2020-08-26
发明人： Richard W. D. Booth
摘要： A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency fCLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2n)×2π radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e., at a rate fCLK, to produce a full-speed serialized digital output having 2n/M samples per cycle, and converts the full-speed serialized digital output to a final output analog waveform of frequency fOUT=(M/2n)×fCLK.
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9.发明授权公开(公告)号：US11115036B1
公开(公告)日：2021-09-07
申请号：US16991882
申请日：2020-08-12
摘要： An oscillator including a switched capacitor configured to generate a sawtooth or ramp voltage in response to a switched capacitor drive signal; a low pass filter (LPF) configured to filter the sawtooth or ramp voltage to generate a filtered voltage; a reference voltage generator configured to generate a reference voltage; an integrator configured to integrate a difference between the sawtooth or ramp voltage and the reference voltage to generate a frequency control signal; a voltage controlled oscillator (VCO) configured to generate a first clock based on the frequency control signal; a frequency divider configured to frequency divide the first clock to generate a second clock; and a switched capacitor driver configured to generate the switched capacitor drive signal in response to the second clock. The oscillator may also include a switched capacitor sampler to sample the sawtooth or ramp voltage, wherein the filtered voltage is based on the sampled voltage.
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公开(公告)号：US20210126643A1
公开(公告)日：2021-04-29
申请号：US17078945
申请日：2020-10-23
发明人： Domenico TRIPODI
摘要： A time measurement includes a multiphase clock generator and a phase sampling circuit. The multiphase clock generator generates a sequence of a given number n of phase shifted clock phases, wherein one of the phase shifted clock phases represents a reference clock signal. The phase sampling circuit is configured to generate a phase value indicative of a number of fractions 1/n of the clock period of the clock phases elapsed between an edge of the reference clock signal and an instant when an asynchronous event signal is set. The phase sampling circuit includes first through fourth sub-circuits, which respectively generate or determine first through fourth control signals.
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