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公开(公告)号：US20170257065A1
公开(公告)日：2017-09-07
申请号：US15191350
申请日：2016-06-23
Applicant: QUALCOMM Incorporated
Inventor： Kevin Wang , Chao Song , Shyam Sivakumar
IPC: H03B5/24
CPC classification number: H03B5/24 , H03B5/26 , H03K3/03 , H03K3/0315 , H03K5/065 , H03K5/1252 , H03L7/099
Abstract: An oscillator circuit having a programmable output frequency may include a first delay section having a negative gain and a variable delay that is set by a control signal provided to the first delay section. A second delay section having a negative gain and a fixed delay may be connected in series with the first delay section. The oscillator circuit may include an output comprising the output of the second delay section having a frequency that is dependent on the delay of the first delay section and the delay of second delay section.
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2.发明授权公开(公告)号：US11115036B1
公开(公告)日：2021-09-07
申请号：US16991882
申请日：2020-08-12
Applicant: QUALCOMM Incorporated
Inventor： Shitong Zhao , Kevin Jia-Nong Wang , Shyam Sivakumar , Debesh Bhatta
Abstract: An oscillator including a switched capacitor configured to generate a sawtooth or ramp voltage in response to a switched capacitor drive signal; a low pass filter (LPF) configured to filter the sawtooth or ramp voltage to generate a filtered voltage; a reference voltage generator configured to generate a reference voltage; an integrator configured to integrate a difference between the sawtooth or ramp voltage and the reference voltage to generate a frequency control signal; a voltage controlled oscillator (VCO) configured to generate a first clock based on the frequency control signal; a frequency divider configured to frequency divide the first clock to generate a second clock; and a switched capacitor driver configured to generate the switched capacitor drive signal in response to the second clock. The oscillator may also include a switched capacitor sampler to sample the sawtooth or ramp voltage, wherein the filtered voltage is based on the sampled voltage.
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公开(公告)号：US20200091918A1
公开(公告)日：2020-03-19
申请号：US16132173
申请日：2018-09-14
Applicant: Qualcomm Incorporated
Inventor： Kevin Jia-Nong Wang , Shyam Sivakumar
Abstract: An apparatus is disclosed that implements frequency synthesis with accelerated locking. In an example aspect, the apparatus includes an oscillating signal source, a modulus compensator, and a frequency generator. The oscillating signal source is configured to provide a reference signal having a reference frequency. The modulus compensator is coupled to the oscillating signal source and is configured to receive the reference signal. The modulus compensator is configured to produce a compensated modulus value based on the reference frequency, a fixed oscillator frequency of a fixed-frequency oscillator signal, and a modulus value. The frequency generator is coupled to the oscillating signal source and the modulus compensator and is configured to receive the compensated modulus value. The frequency generator is configured to generate an output signal having an output frequency that is based on the reference frequency and the compensated modulus value.
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公开(公告)号：US09755575B1
公开(公告)日：2017-09-05
申请号：US15191350
申请日：2016-06-23
Applicant: QUALCOMM Incorporated
Inventor： Kevin Wang , Chao Song , Shyam Sivakumar
IPC: H03K3/03 , H03B5/24 , H03L7/099 , H03K5/1252 , H03K5/06
CPC classification number: H03B5/24 , H03B5/26 , H03K3/03 , H03K3/0315 , H03K5/065 , H03K5/1252 , H03L7/099
Abstract: An oscillator circuit having a programmable output frequency may include a first delay section having a negative gain and a variable delay that is set by a control signal provided to the first delay section. A second delay section having a negative gain and a fixed delay may be connected in series with the first delay section. The oscillator circuit may include an output comprising the output of the second delay section having a frequency that is dependent on the delay of the first delay section and the delay of second delay section.
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