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Patent Agency Ranking
公开(公告)号：US20160156363A1
公开(公告)日：2016-06-02
申请号：US15014905
申请日：2016-02-03
Inventor： TSUNG-HSIEN TSAI
CPC classification number: G04F10/005 , H03L7/085 , H03L2207/18 , H03L2207/50
Abstract: A circuit includes a reset circuit, a counter and a comparator. The reset circuit generates a reset signal based on a reference signal and a controlled signal. The reference signal and the controlled signal are to be sent to the TDC for detection of phase difference. The counter counts to a predetermined value associated with the reference signal and the controlled signal, and is reset to an initial value in response to the reset signal. The comparator compares a count from the counter and the predetermined value, and generates a mask signal when a count from the counter equals the predetermined value. The mask signal masks a portion of pulses of the controlled signal from entering the TDC.
Abstract translation: 电路包括复位电路，计数器和比较器。 复位电路基于参考信号和受控信号产生复位信号。 将参考信号和受控信号发送到TDC以检测相位差。 计数器计数到与参考信号和受控信号相关联的预定值，并且响应于复位信号被复位到初始值。 比较器比较来自计数器的计数和预定值，并且当来自计数器的计数等于预定值时产生掩码信号。 屏蔽信号屏蔽受控信号的一部分脉冲进入TDC。
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公开(公告)号：US20170093411A1
公开(公告)日：2017-03-30
申请号：US14871602
申请日：2015-09-30
Inventor： TSUNG-HSIEN TSAI , CHIH-HSIEN CHANG
CPC classification number: H03L7/0994 , H03K7/06 , H03L2207/50
Abstract: A frequency scaling method is disclosed. The method is used for changing an output frequency of an all-digital phase-locked loop (ADPLL) from a first frequency to a second frequency different from the first frequency. The method includes: stopping a feeding of a first oscillator tuning word (OTW) to a digitally controlled oscillator (DCO) of the ADPLL, wherein the first OTW is generated based on a phase detecting result obtained with respect to the first frequency; feeding a second OTW to the DCO in order to change the output frequency from the first frequency to the second frequency; and performing a zero phase restart (ZPR) operation to produce the phase detecting result according to the second frequency. An associated ADPLL and a frequency scaling circuit are also disclosed.
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公开(公告)号：US20160072514A1
公开(公告)日：2016-03-10
申请号：US14497890
申请日：2014-09-26
Inventor： TSUNG-HSIEN TSAI
CPC classification number: H03L7/0995 , H03B27/00 , H03K3/011 , H03K5/133 , H03L1/00 , H03L7/0802 , H03L7/093 , H03L7/099 , H03L7/0994 , H03L7/0997 , H03L2207/50
Abstract: In some embodiments, a digitally controlled oscillator includes a first oscillator a second oscillator and a switch. The second oscillator is selectively enabled in response to a controlled signal. The switch is coupled between the first oscillator and the second oscillator and is selectively conducted in response to the controlled signal, so that an oscillator signal is provided by the first oscillator when the switch is not conducted, and provided by the first oscillator and the second oscillator when the switch is conducted.
Abstract translation: 在一些实施例中，数字控制振荡器包括第一振荡器，第二振荡器和开关。 响应于受控信号，第二振荡器被选择性地使能。 开关耦合在第一振荡器和第二振荡器之间并且响应于受控信号选择性地导通，使得当开关不导通时由第一振荡器提供振荡器信号，并且由第一振荡器和第二振荡器提供振荡器信号 当开关导通时振荡器。
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公开(公告)号：US20150194971A1
公开(公告)日：2015-07-09
申请号：US14149149
申请日：2014-01-07
Inventor： TSUNG-HSIEN TSAI
IPC: H03L7/193
CPC classification number: G04F10/005 , H03L7/085 , H03L2207/18 , H03L2207/50
Abstract: A time-to-digital converter (TDC) comprises a TDC core and a masking circuit. The TDC core is configured to detect phase difference between a reference signal and a controlled signal. The masking circuit is configured to generate a mask signal based on the reference signal, the controlled signal, and a command signal including information of a predetermined value associated with the reference signal and the controlled signal. The mask signal is used to mask a portion of pulses of the controlled signal from entering the TDC core during detection of phase difference.
Abstract translation: 时间数字转换器（TDC）包括TDC内核和屏蔽电路。 TDC内核被配置为检测参考信号和受控信号之间的相位差。 掩蔽电路被配置为基于参考信号，受控信号和包括与参考信号和受控信号相关联的预定值的信息的命令信号来生成屏蔽信号。 屏蔽信号用于在检测相位差期间屏蔽受控信号的一部分脉冲进入TDC内核。
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公开(公告)号：US20230361762A1
公开(公告)日：2023-11-09
申请号：US18352286
申请日：2023-07-14
Inventor： RUEY-BIN SHEEN , TSUNG-HSIEN TSAI , CHIH-HSIEN CHANG
Abstract: An electrical system is provided. The electrical system comprises a first phase lock circuit embedded within a first chip for receiving a first periodic signal having a first frequency. The electrical system comprises a first buffering circuit embedded within the first chip for receiving a second periodic signal having the first frequency, wherein the first buffering circuit is configured to provide a third periodic signal having the first frequency to an output terminal of the first chip.
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