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公开(公告)号：US08742810B2
公开(公告)日：2014-06-03
申请号：US13461101
申请日：2012-05-01
申请人： Hiroki Noguchi , Keiko Abe , Shinichi Yasuda , Shinobu Fujita
发明人： Hiroki Noguchi , Keiko Abe , Shinichi Yasuda , Shinobu Fujita
IPC分类号： H03L7/06
CPC分类号： H03L7/14 , H03L2207/18
摘要： One embodiment provides a phase-locked loop (PLL), in which a sequencer controls a loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of a first resistance change device in the loop filter is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value.
摘要翻译： 一个实施例提供了一种锁相环（PLL），其中定序器控制环路滤波器，使得当指示关闭PLL的电源的信号被输入时，或者当指示接通 PLL的电源被输入到其中，环路滤波器中的第一电阻改变装置的电阻值是第一电阻值，并且在PLL稳定之后，第一电阻改变装置的电阻值是第二电阻值 电阻值高于第一电阻值。
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公开(公告)号：US07050520B2
公开(公告)日：2006-05-23
申请号：US10152851
申请日：2002-05-23
申请人： Hideyuki Asakawa , Yoshimasa Endou
发明人： Hideyuki Asakawa , Yoshimasa Endou
IPC分类号： H04L7/00
CPC分类号： H03L7/18 , H03L2207/18
摘要： If a phase difference between a synchronizing source signal F1 and a comparison signal F2 is higher than a first lower limit a or lower than a first upper limit b, a comparator 3 selects this phase difference, if the phase difference is not higher than the lower limit a, selects the lower limit a, and if the phase difference is not lower than the upper limit b, selects the upper limit b, and a divider 7A outputs a comparison signal F2 obtained by dividing a frequency of an output signal F0, to change a phase of the signal F2 so that if the phase difference is not higher than a second lower limit e lower than the lower limit a, the phase difference may become the lower limit a and, if the phase difference is higher than a second upper limit f higher than the upper limit b, the phase difference may become the upper limit b.
摘要翻译： 如果同步源信号F 1和比较信号F 2之间的相位差高于第一下限a或低于第一上限b，则比较器3选择该相位差，如果相位差不高于 下限a选择下限a，如果相位差不低于上限b，则选择上限b，分频器7A输出通过将输出的频率除以所得到的比较信号F 2 信号F 0，以改变信号F 2的相位，使得如果相位差不高于低于下限a的第二下限e，则相位差可以变为下限a，并且如果相位差 高于上限b的第二上限f时，相位差可能成为上限b。
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公开(公告)号：US06965660B2
公开(公告)日：2005-11-15
申请号：US09969269
申请日：2001-09-28
申请人： Klaus Strohmayer
发明人： Klaus Strohmayer
CPC分类号： H03L7/199 , H03L7/0991 , H03L7/10 , H03L2207/18 , H03L2207/50
摘要： A digital phase-locked loop is provided having a minimal transient recovery time for emitting an output clock signal which is synchronous with a reference clock signal in a normal operating state of the digital phase-locked loop. The phase-locked loop can include a phase detector for identifying a phase deviation between the reference clock signal and a feedback clock signal. Further, the phase-locked loop can include a resettable counter, which generates a digital phase deviation signal corresponding to the identified phase deviation. The phase-locked loop can also include a resettable digital filter for filtering the digital phase deviation signal. Further, the phase-locked loop can include an oscillator circuit for generating the output clock signal as a function of a filtered digital phase deviation signal. The phase-locked loop can also include a resettable feedback frequency divider which divides the output clock signal for generating the feedback clock signal.
摘要翻译： 提供数字锁相环，具有最小的瞬态恢复时间，用于在数字锁相环的正常工作状态下发射与参考时钟信号同步的输出时钟信号。 锁相环可以包括用于识别参考时钟信号和反馈时钟信号之间的相位偏差的相位检测器。 此外，锁相环可以包括可复位计数器，其产生对应于所识别的相位偏差的数字相位偏差信号。 锁相环还可以包括用于滤波数字相位偏差信号的可复位数字滤波器。 此外，锁相环可以包括用于根据滤波的数字相位偏差信号产生输出时钟信号的振荡器电路。 锁相环还可以包括可复位的反馈分频器，其分频输出时钟信号以产生反馈时钟信号。
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4.发明申请公开(公告)号：US20040113665A1
公开(公告)日：2004-06-17
申请号：US10688208
申请日：2003-10-17
发明人： Loic Joet , Sebastien Dedieu , Eric Andre , Daniel Saias
IPC分类号： H03L007/06
CPC分类号： H03L7/087 , H03L7/0891 , H03L7/183 , H03L7/199 , H03L2207/18
摘要： A method for generating a signal with a frequency equal to a product of a reference frequency and a real number includes providing an output signal from an oscillator, and performing a first integer division of a frequency of the output signal by a first integer divider to obtain a first intermediate signal. A first measurement signal representative of a time difference between the first intermediate signal and a reference signal having the reference frequency is determined. The method further includes generating a first comparison signal derived from the first measurement signal, and generating a second comparison signal dependent on a period of the reference signal, on integer and decimal parts of the real number and on the first integer divider. The first and second comparison signals are compared to obtain an error signal representative of a time difference between a period of a current output signal and the period of the reference signal. The first integer division is deactivated to deliver an error signal to the input of the oscillator, with the output signal from the oscillator forming the desired signal with a frequency equal to the product of the reference frequency and the real number.
摘要翻译： 用于产生频率等于参考频率和实数的乘积的信号的方法包括提供来自振荡器的输出信号，以及通过第一整数分频器对输出信号的频率进行第一整数除法以获得 第一中间信号。 确定代表第一中间信号和具有参考频率的参考信号之间的时间差的第一测量信号。 该方法还包括生成从第一测量信号导出的第一比较信号，以及根据参考信号的周期，在实数的整数和小数部分以及第一整数分频器上产生第二比较信号。 比较第一和第二比较信号以获得表示当前输出信号的周期与参考信号周期之间的时间差的误差信号。 第一个整数除法被去激活以向振荡器的输入端发送一个误差信号，来自振荡器的输出信号形成期望的信号，其频率等于参考频率和实数的乘积。
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5.发明授权公开(公告)号：US06574287B1
公开(公告)日：2003-06-03
申请号：US09491875
申请日：2000-01-27
IPC分类号： H04L2706
CPC分类号： H03L7/0891 , H03D11/02 , H03D13/004 , H03L7/14 , H03L7/18 , H03L2207/18 , H04L27/02 , H04L2027/0055
摘要： Disclosed is a frequency-locked loop (FLL), which attempts to bring about frequency and phase synchronization between two signals over the control bandwidth of the loop: a reference signal and a voltage-controlled oscillator (VCO) signal. For example, the FLL employs a reference signal generated by a crystal oscillator of frequency fREF and a VCO signal generated by the oscillations of an unquenched SRG resonator with tunable resonant frequency fRES. These signals are connected to the inputs of a phase/frequency detector (PFD) which produces output pulses in response to the relationship between fREF and fRES. These pulses are applied to a loop filter (LF) which creates a voltage using some kind of charge-storage element. This loop filter voltage is a so-called error voltage whose value is used to control the frequency of the resonator to bring the reference signal and VCO signal into phase synchrony.
摘要翻译： 公开了一种频率锁定环（FLL），其试图在环路的控制带宽上引起两个信号之间的频率和相位同步：参考信号和压控振荡器（VCO）信号。 例如，FLL采用由频率fREF的晶体振荡器产生的参考信号和由具有可调谐谐振频率fRES的未衰减的SRG谐振器的振荡产生的VCO信号。 这些信号连接到相位/频率检测器（PFD）的输入端，该相位/频率检测器响应于fREF和fRES之间的关系产生输出脉冲。 这些脉冲被施加到使用某种电荷存储元件产生电压的环路滤波器（LF）。 该环路滤波器电压是所谓的误差电压，其值用于控制谐振器的频率，使参考信号和VCO信号同相。
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公开(公告)号：US20020118053A1
公开(公告)日：2002-08-29
申请号：US10107553
申请日：2002-03-26
IPC分类号： H03L007/06
CPC分类号： H03L7/199 , H03L7/0802 , H03L7/087 , H03L7/0891 , H03L7/0898 , H03L7/095 , H03L7/107 , H03L7/1077 , H03L7/183 , H03L7/191 , H03L2207/04 , H03L2207/18
摘要： The PLL device includes means (6) for generating a, plurality of reference signals (FR1, FR2, FR3, FR4) having mutually differing phases, a variable frequency divider (11, 12, 13, 14) for dividing, in synchronization with the phases of a plurality of the reference signals, a frequency of an output signal (FO) of a voltage-controlled oscillator (15) that produces a signal having a frequency responsive to a control voltage (CV) supplied to generate a plurality of feedback signals (FV1, FV2, FV3, FV4) having mutually differing phases, phase comparators (7, 17, 8, 18, 9, 19, 10, 20) for comparing phases between the reference signals and the feedback signals corresponding to the reference signals respectively to produce a plurality of error signals (ER1, ER2, ER3, ER4), a low-pass filter (21) for filtering the error signals output from the phase comparators to produce the control voltage, and a control means (16, 26, 27) for controlling the number of the phase comparators that output the error signals to the low-pass filter in accordance with a phase difference between at least one of a plurality of the feedback signals and the reference signal corresponding to the one of a plurality of the feedback signals.
摘要翻译： PLL装置包括用于产生具有相互不同相位的多个参考信号（FR1，FR2，FR3，FR4）的装置（6），用于与所述第二信号同步地分配的可变分频器（11,12,13,14） 多个参考信号的相位，压控振荡器（15）的输出信号（FO）的频率，其产生响应于提供的控制电压（CV）的频率的信号，以产生多个反馈信号 具有相互不同相位的相位比较器（FV1，FV2，FV3，FV4），用于分别对应于参考信号的参考信号和反馈信号之间的相位的相位比较器（7,17,8,18,9,19,10,20） 产生多个误差信号（ER1，ER2，ER3，ER4），用于对从相位比较器输出的误差信号进行滤波以产生控制电压的低通滤波器（21），以及控制装置（16,26， 27），用于控制输出呃的相位比较器的数量 根据多个反馈信号中的至少一个与对应于多个反馈信号之一的参考信号之间的相位差，ror向低通滤波器发送信号。
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7.发明授权Means for the production of a voltage which depends upon the difference between two frequencies 失效用于产生取决于两个频率之间的差异的电压的装置
公开(公告)号：US3164777A
公开(公告)日：1965-01-05
申请号：US771560
申请日：1960-02-09
发明人： GUSTAV GUANELLA
CPC分类号： H04L7/033 , H03L7/10 , H03L7/199 , H03L2207/18
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公开(公告)号：US20130027093A1
公开(公告)日：2013-01-31
申请号：US13461101
申请日：2012-05-01
申请人： Hiroki NOGUCHI , Keiko Abe , Shinichi Yasuda , Shinobu Fujita
发明人： Hiroki NOGUCHI , Keiko Abe , Shinichi Yasuda , Shinobu Fujita
CPC分类号： H03L7/14 , H03L2207/18
摘要： One embodiment provides a phase-locked loop (PLL), in which a sequencer controls a loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of a first resistance change device in the loop filter is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value.
摘要翻译： 一个实施例提供了一种锁相环（PLL），其中定序器控制环路滤波器，使得当指示关闭PLL的电源的信号被输入时，或者当指示接通 PLL的电源被输入到其中，环路滤波器中的第一电阻改变装置的电阻值是第一电阻值，并且在PLL稳定之后，第一电阻改变装置的电阻值是第二电阻值 电阻值高于第一电阻值。
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公开(公告)号：US06961399B2
公开(公告)日：2005-11-01
申请号：US09867971
申请日：2001-05-30
申请人： Jong-haeng Lee
发明人： Jong-haeng Lee
CPC分类号： H03L7/23 , H03L7/199 , H03L2207/18
摘要： A PLL circuit includes a control circuit for generating a reference control signal. A reception divider, reference divider, and transmission divider respectively divide an output signal of a receiver VCO according to a reception division data signal, an output signal of a crystal oscillator according to a reference division data signal, and an output signal of a transmitter VCO according to a transmission division data signal. A first and second phase detector respectively detect frequency and phase differences between a reception divider output and a reference divider output and between a transmission divider output and the reference divider output.
摘要翻译： PLL电路包括用于产生参考控制信号的控制电路。 接收分频器，参考分频器和发送除法器根据接收分频数据信号，根据参考分频数据信号将晶体振荡器的输出信号和发射机VCO的输出信号分别分开接收器VCO的输出信号 根据传输分割数据信号。 第一和第二相位检测器分别检测接收分配器输出和参考分压器输出之间以及传输分压器输出和参考分压器输出之间的频率和相位差。
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公开(公告)号：US06904113B2
公开(公告)日：2005-06-07
申请号：US10017888
申请日：2001-12-12
申请人： Markku Ruuskanen
发明人： Markku Ruuskanen
CPC分类号： H03L7/08 , H03L7/143 , H03L7/18 , H03L2207/18 , H04J3/0688
摘要： The invention concerns a function taking place in a digital phase lock, when it is desired to exchange a synchronization signal supplied to the phase lock for another synchronization signal. Using a cut-off circuit, the phase difference between a selected reference signal and a signal formed by dividing from an oscillator signal is set with time constant accuracy at the setting value for the phase difference. The method according to the invention, then uses as phase setting value the current value of the phase difference obtained by cut-off connection. Thus, the method according to the invention begins using a reference signal-specific setting value instead of a fixed setting value. Since the setting value is determined adaptively in accordance with the signal of the synchronization source used at each time, no phase transfer will occur during the change.
摘要翻译： 当需要交换提供给相位锁的同步信号以用于另一个同步信号时，本发明涉及在数字锁相中发生的功能。 使用截止电路，以相位差的设定值的时间常数精度设定所选择的基准信号与由振荡器信号分割的信号之间的相位差。 根据本发明的方法，然后将相位设定值用作通过切断连接获得的相位差的当前值。 因此，根据本发明的方法开始使用参考信号特定设置值而不是固定设置值。 由于根据每次使用的同步源的信号自适应地确定设定值，所以在改变期间不会发生相位转移。
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