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公开(公告)号：US10686474B1
公开(公告)日：2020-06-16
申请号：US16454749
申请日：2019-06-27
发明人： Roee Ben-Yishay
摘要： One illustrative dual mode frequency multiplier embodiment includes: a first and a second nonlinear element, a summation node, and a switchable phase shifter. The first and second nonlinear elements are driven by a differential signal to produce a first and a second branch signal each having even and odd harmonics, the even harmonics being in-phase and the odd harmonics being out of phase. The first and second branch signals combine at the summation node to form a combined signal. The switchable phase shifter couples the first nonlinear element to the summation node, providing the first branch signal with a phase shift switchable between 0 and 180° to suppress either the odd or the even harmonics from the combined signal.
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公开(公告)号：US10447203B2
公开(公告)日：2019-10-15
申请号：US15860951
申请日：2018-01-03
申请人： FCI INC.
发明人： Jecheol Moon
摘要： A local oscillator generation system includes a first frequency divider configured to divide frequencies of a first voltage controlled oscillator signal and a second voltage controlled oscillator signal by 2, and output a first divided signal and a second divided signal; a mixer configured to mix the first voltage controlled oscillator signal, the second voltage controlled oscillator signal, the first divided signal, and the second divided signal, and output a first frequency mixed signal and a second frequency mixed signal; a transimpedance amplifier configured to amplify the first frequency mixed signal and the second frequency mixed signal, and output a first amplified signal and a second amplified signal; and a band-pass filter configured to filter the first amplified signal and the second amplified signal, and output a first filtered signal and a second amplified signal.
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公开(公告)号：US10389303B2
公开(公告)日：2019-08-20
申请号：US15921480
申请日：2018-03-14
申请人： Rambus Inc.
发明人： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
摘要： Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
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4.发明授权公开(公告)号：US10199988B2
公开(公告)日：2019-02-05
申请号：US15538642
申请日：2015-12-22
发明人： Geon Ho An , In Sun Choi , Dong Jun Won , Jin Young Choi , Jin Sun Yang
摘要： The present invention relates to a power management system (PMS) for multiple energy storage systems (ESS) that is for integrated management of the system having multiple ESS for controlling a frequency and having a hierarchical control structure. The PMS for ESS comprises: a plurality of ESS; a local management system (LMS) for managing one or more ESS of the plurality of ESS for each local unit; an ESS Controller (ESSC) for general management of the LMS, judging a state of the LMS and determining an output value of one or more ESS in the LMS, and transmitting the determined output value to the respective ESS; and a PMS for general management of the entire system comprising the plurality of ESS, the LMS and the ESSC, judging the state of the entire system and participating in a power grid frequency control market through a grid operator contract, controlling the output of the LMS, and adjusting a control parameter for output control.
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公开(公告)号：US20180278210A1
公开(公告)日：2018-09-27
申请号：US15921480
申请日：2018-03-14
申请人： Rambus Inc.
发明人： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
CPC分类号： H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099 , H05K999/99
摘要： Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
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公开(公告)号：US09973177B1
公开(公告)日：2018-05-15
申请号：US15360149
申请日：2016-11-23
申请人： Rambus Inc.
发明人： Yue Lu , Jared L. Zerbe
CPC分类号： H03K5/00006 , H03J2200/10 , H03L7/0802 , H03L7/083 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/16 , H03L7/24 , H04L7/033
摘要： In a clock generating circuit having a plurality of injection-locking oscillators, a first one of the injection-locking oscillators is enabled to output a free-running reference clock signal and a control value is generated based at least in part on a frequency relationship between the free-running reference clock signal and an input timing signal. In accordance with the control value, a selected one of the injection-locking oscillators is enabled to generate an output clock signal that is frequency-locked with respect to the input timing signal.
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公开(公告)号：US20170126238A1
公开(公告)日：2017-05-04
申请号：US15402300
申请日：2017-01-10
发明人： Igal Kushnir , Hung-Ming Chen , Wei-Hong Chen , Theodoros Chalvatzis , Seunghwan Yoon , Chin-Ming Chen , Tirdad Sowlati , Moche Cohen , Kobi Sturkovich , Shaul Klein
摘要： A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.
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8.发明授权公开(公告)号：US09515609B1
公开(公告)日：2016-12-06
申请号：US14986421
申请日：2015-12-31
发明人： Frederic Rivoirard
IPC分类号： H03B19/00 , G06F7/44 , H03D7/14 , H03K5/1252
CPC分类号： H03D7/1466 , H03D7/1441 , H03D7/1458 , H03D2200/0088 , H03K5/1252
摘要： A signal generation circuit includes a voltage controlled oscillator configured to generate a differential oscillator signal having an amplitude. A passive mixer has first differential inputs coupled to the voltage controlled oscillator to receive the oscillator signal. The passive mixer also includes second differential inputs. A filter circuit is coupled between the voltage controlled oscillator and the second differential inputs of the passive mixer. The filter circuit is configured to filter the differential oscillator signal as a function of the amplitude of the differential oscillator signal to thereby generate a filtered differential oscillator signal and to provide the filtered differential oscillator signal to the second differential inputs of the passive mixer.
摘要翻译： 信号发生电路包括被配置为产生具有振幅的差分振荡器信号的压控振荡器。 无源混频器具有耦合到压控振荡器的第一差分输入端以接收振荡器信号。 无源混频器还包括第二差分输入。 滤波电路耦合在压控振荡器和无源混频器的第二差分输入端之间。 滤波器电路被配置为根据差分振荡器信号的幅度对差分振荡器信号进行滤波，从而产生经滤波的差分振荡器信号，并将经滤波的差分振荡器信号提供给无源混频器的第二差分输入。
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公开(公告)号：US09509293B2
公开(公告)日：2016-11-29
申请号：US13870744
申请日：2013-04-25
发明人： Xiangpeng Li , Yu Liu , Cong Yao
CPC分类号： H03K5/00006 , G06F1/206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Embodiments of the present invention disclose a method and an apparatus for controlling chip performance, and relate to the field of communications technologies, which solves a problem in the prior art that a chip is reset or performance is greatly decreased as long as a temperature of the chip is higher than a preset threshold. The method includes: obtaining a working temperature of a chip; when the working temperature of the chip reaches one of multiple preset temperature thresholds, obtaining, according to preset correspondence between a temperature threshold and a chip performance control policy, a chip performance control policy that corresponds to the one of the multiple temperature thresholds; and controlling working of the chip according to the control policy. The present invention is applicable to an electronic device to which a chip is applied, such as a desktop computer or a notebook computer.
摘要翻译： 本发明的实施例公开了一种用于控制芯片性能的方法和装置，并且涉及通信技术领域，其解决了现有技术中芯片复位或性能大大降低的问题，只要温度 芯片高于预设阈值。 该方法包括：获得芯片的工作温度; 当芯片的工作温度达到多个预设温度阈值之一时，根据温度阈值与芯片性能控制策略之间的预设对应关系获得对应于多个温度阈值之一的芯片性能控制策略; 并根据控制策略控制芯片的工作。 本发明可应用于应用芯片的电子设备，例如台式计算机或笔记本计算机。
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公开(公告)号：US09369135B2
公开(公告)日：2016-06-14
申请号：US13846171
申请日：2013-03-18
CPC分类号： H03L7/06
摘要： Systems and methods for generating gapped signals comprising a Delta Sigma Modulator (DSM) configured to generate gapping control signals used to control gap removal rates of an associated gapping unit. The DSM is configured to generate a gapping control signal based on a value of an overflow resulted from performing adding a first number with a remainder of a stored value modulo a second number. The gap removal rates as well as the gap removal resolutions can be adjusted by selecting appropriate values of the first number, the stored value, and the second number. The gapping resolution can be a portion of a pulse. The first number and the second number may be derived from an intended frequency ratio between a gapped signal and a corresponding input signal. The gapping unit may comprise a gapping circuit or a multi-modulus divider.
摘要翻译： 用于产生有间隙信号的系统和方法包括配置成产生用于控制相关间隙单元的间隙去除速率的间隙控制信号的ΔΣ调制器（DSM）。 DSM被配置为基于通过执行将具有第二数量的存储值的剩余部分的第一数字相加的溢出的值来生成间隙控制信号。 可以通过选择第一个数字，存储值和第二个数字的适当值来调整间隙去除率以及间隙去除分辨率。 间隙分辨率可以是脉冲的一部分。 第一数字和第二数字可以从有间隙信号和对应的输入信号之间的预期频率比率导出。 间隙单元可以包括间隙电路或多模式分配器。
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